Samsung Electronics Co., Ltd.

Seung-Hwan Song

Jun Jin Kong

Kyoung Lae Cho

Sung Chung Park

Dong Hyuk Chae

Heeseok Eun

Jae Hong Kim

Yoon-Dong Park

Young Hwan Lee

Sung-Jae Byun

Nam Phil Jo

Seung Jae Lee

Jong Han Kim

Jun-Jin Kong

Suk-Pil Kim

Jae-woong Hyun

Yoon Dong Park

Kyoung-Lae Cho

Jae-Hong Kim

Won-Joo Kim

Yong June Kim

June-mo Koo

Dong Ku Kang

Han Woong Yoo

Jaehong Kim

Dongku Kang

Ju-hee Park

Hong Rak Son

Junjin Kong

Seung Hoon Lee

Seung-hoon Lee

Dong-Hyuk Chae

Il-Han Park

Yong-June Kim

Yoon Sun Park

Jong-jin Lee

Tae Hun Kim

Seung-Jae Lee

Choong-Ho Lee

Jung-Hoon Lee

Young-Gu Jin

Tae-hun Kim

Kyu-Charn Park

Dong-Ku Kang

Young-Hwan Lee

Jong-han Kim

Seung-Hoon Lee

Hee Seok Eun

KyoungLae Cho

Yoon-dong Park

Dong Hun Yu

Kyoung-Iae Cho

Na-Young Choi

Donghun Yu

Han-woong Yoo

Hee-seok Eun

Hyun-jun Yoon

Young-Moon Kim

Ju-Hee Park

Jung Hun Sung

Sung-chung Park

Sung-Chung Park

Young-moon Kim

Kyong Lae Cho

In a method of operating a nonvolatile memory device including a memory cell array, where the memory cell array includes a plurality of pages, and each of the plurality of pages includes a plurality of nonvolatile memory cells, a first sampling read operation is performed to count a first number of memory cells in a first region of a first page selected from the plurality of pages, using a first default read voltage and a first offset read voltage, and a second sampling read operation is selectively performed to count a second number of memory cells in a second region of the first page, using the first default read voltage and a second offset read voltage, based on a comparison result of the first number and a first reference value. The second offset read voltage is different from the first offset read voltage.

Methods of operating a nonvolatile memory device and the nonvolatile memory device thereof

Provided is a read method for a nonvolatile memory device for reading data with an optimum read voltage. The read method includes reading data of a first set of memory cells connected to a first word line, by dividing the data of the first set of memory cells into M pages and individually reading data from the M pages. The reading data includes performing an on-chip valley search (OVS) operation on a first valley of two adjacent threshold voltage distributions of the first set of memory cells when reading each of the M pages, and performing a data recover read operation via a read operation on a second word line adjacent to the first word line, based on a result of the OVS operation. In the data recover read operation, a read operation on the first word line is not performed.

Non-volatile memory device for reading data with optimized read voltage

A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data

Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected sub-distribution from among a plurality of sub-distributions according to a distance of the threshold voltage variation of the first memory cell, the plurality of sub-distributions corresponding to a target distribution of the second memory cell.

Access method of non-volatile memory device

Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

Memory device and error control codes decoding method

According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.

Apparatus for generating soft decision values using an analog-to-digital converter and method thereof

A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.

Nonvolatile memory device and read method using dynamically determined read voltages

A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.

Method of setting read voltage minimizing read data errors

The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nbits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nbits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nbits of the data are completely programmed or read, programs or reads an (N+1)bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nbits of the data, to program or read for 2cell distributions of 2cell distributions corresponding to the (N+1)bit of the data and then programs or reads for other 2cell distributions.

Flash memory device, programming and reading methods performed in the same

Disclosed is a program method of a non-volatile memory device which comprises classifying plural memory cells into aggressor cells and victim cells based on program data to be written in the plural memory cells; and programming the aggressor cells by a program manner different from the victim cells.

Non-volatile memory device and program method thereof

Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.

Memory device and method for estimating characteristics of multi-bit programming

A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.

Apparatus and method of memory programming

Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.

Apparatus for determining number of bits to be stored in memory cell

Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same

A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n&#xb7;p-bit code based on at least one of the input information and the delayed information, where n is a rational number.

Apparatuses and methods for encoding and decoding

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Incheon, South Korea

Seung-Hwan Song