Samsung Electronics Co., Ltd.

Lg Hausys, Ltd.

Ls Mtron Ltd.

Seung-Hun Lee

Yun-Ho Choi

Hyun-Soon Jang

Ho-cheol Lee

Byeong-Chan Lee

Si-Yeol Lee

Tae-jin Kim

Churoo Park

Myung-Ho Kim

Chull-Soo Kim

Nam-Soo Kang

Soo-In Cho

Dae-je Chin

Seung-Moon Yoo

Ejaz Ul Haq

Sang-Bom Kang

Sun-Ghil Lee

Si-Young Choi

Jin-bum Kim

Joonho Kim

Jun-Young Choi

Minhyung Kim

Deok-hyung Lee

Dong-Il Back

Ji-Yong Park

Kwan-Heum Lee

Han-Na Lee

Ick-kyun Lee

Keon-cheol Park

In-duck Song

Geo-Hyeok Lim

Byoungwoong An

Seongwoo Yi

Provided is a washing machine including a main body having a first inlet, a drum arranged inside the main body to accommodate laundry, and a door configured to open and close the first inlet, wherein the door includes a second inlet to allow laundry to be introduced into the drum while the first inlet closed, an auxiliary door configured to open and close the second inlet, and a restraining device configured to restrain the auxiliary door such that the auxiliary door remains locked onto the door, and the main body includes a pressing device arranged inside the main body and configured to press the restraining device such that the restraining device locks the auxiliary door and to release from the retraining device such that the restraining device unlocks the auxiliary door.

Washing machine

Provided are a decoration sheet and a method for producing same. The decoration sheet sequentially includes a thermosetting resin layer, a deposition layer, and a base layer. The thermosetting resin layer has a micropattern on a surface thereof, and the elongation rate of the sheet is 200% to 300%. The method includes forming a photocurable imprint film having a first pattern on a first surface thereof, forming a thermosetting resin layer having a second pattern, which has a reverse phase to the first pattern, on a first surface thereof, forming a deposition layer on a second surface of the thermosetting resin layer, forming a substrate layer on one surface of the deposition layer, and releasing the photocurable imprint film from the thermosetting resin layer.

Method for producing decoration sheet having micropattern

Disclosed is a photoelectric wiring module which includes: a substrate; a frame mounted on the substrate; an optical device package configured to perform photoelectric conversion or electro-optic conversion of a signal; an optical control device configured to control an operation of the optical device package; and an optical transmission line configured to transmit an optical signal that is emitted from the optical device package or incident on the optical device package. Electrical terminals are disposed on the frame, the optical device package is mounted on the frame, and the optical control device is disposed within the frame and mounted on the substrate.

Photoelectric wiring module

A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

Semiconductor devices

Methods of manufacturing semiconductor devices

A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

Methods of manufacturing a semiconductor device

A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

Semiconductor memory devices having vertical channel transistors and related methods

A digital locked loop circuit having a synchronous delay line, an input node for receiving an external clock signal, and an internal clock node for generating an internal clock signal synchronized with the external clock signal. The digital locked loop circuit includes; a delay buffer for generating a first clock signal by delaying the external clock signal by a predetermined time; a main delay for generating a second clock signal by delaying the first clock signal by a predetermined time; a first delay line consisting of a plurality of serially connected first unit delays, each of the plurality of first unit delays generating a first unit delay output signal by delaying the second clock signal by a predetermined unit length; a second delay line consisting of a plurality of serially connected second unit delays, each of the plurality of second unit delays generating a second unit delay output signal by delaying the first clock signal by a predetermined unit length; switching means for coupling the first clock signal to the internal clock node in response to an enable signal, the switching means having a plurality of switches, each of the plurality of switches connected between an output node of a corresponding second unit delay of the second delay line and the internal clock node; and phase comparing means for generating the enable signal for a predetermined switch of the plurality of switches when the first clock signal is in phase with at least one first unit delay output signal, the phase comparing means being connected between an output node of a first unit delay and an enable port of a corresponding switch of the plurality of switches of the switching means.

Digital delay locked loop circuit using synchronous delay line

A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Semiconductor memory device

A redundancy circuit for activating redundant memory cells when a semiconductor memory device is found to have defective memory cells, which redundancy circuit comprises, in order to overcome the problems of an address reset and a precharging of the first node which determines the redundancy addressing output signal of the redundancy circuit, additional switching circuit which is controlled by a clock signal of the memory device being made to be connected between a ground node and a switching circuit connected to a plurality of fuses, and a precharging circuit for precharging the first node to a high voltage level being made to also controlled by the clock signal.

Redundancy circuit for memory devices having high frequency addressing

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Circuit in a semiconductor memory for programming operation modes of the

Synchronous dram having a plurality of latency modes

A bit line sensing circuit of a semiconductor memory device is disclosed which includes a pull-up control signal generator that enables the peak current to be small by supplying to the P sense amplifier a pull-up voltage of the low level in an initial sensing process. When the peak current is stabilized, the pull-up control signal generator then reduces the time required for raising the pull-up voltage by very quickly raising the voltage of the pull-up control signal. This results in the advantages that the peak current can be greatly reduced without slowing sensing speed, and voltage noise caused from peak currents can be eliminated.

Bit line sensing circuit of a semiconductor memory device

System for selecting one of a plurality of memory banks for use in an

Growing community of inventors

Suwon, South Korea

Seung-Hun Lee