Samsung Electronics Co., Ltd.

Seung Hoon Jung

Hee Sung Chae

Kyung-Min Kim

Hyeok Jong Lee

Hyuk Jun Oh

Woong Joo

Sung Yong Kim

Kyung Min Kim

Sun Jung Kim

Han Soo Lee

Dah Som Kim

An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

Image sensor and method of operating an image sensor

Analog-digital converter and image sensor including thereof

An image sensor includes; a sensor array generating a pixel signal, a ramp signal generator generating a ramp signal having a decreasing slope during a ramp signal enable period between a first time at which a counter enable signal is activated and a third time at which the ramp signal ends falling, a comparator comparing the pixel signal with the ramp signal to trigger an output signal, and counters, where at least one of the counters performs counting during an entire counter enable period extending between the first time and a second time at which the comparator triggers the output signal, but not all of the counters perform counting during at least one section of the counter enable period.

Image sensor and method of operating same

The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

Image sensor for distributing output peak current and image processing system including the same

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Yongin-si, South Korea

Seung Hoon Jung