Hynix Semiconductor Inc.

Seung-Ho Pyi

Yong-Soo Kim

Hong-Seon Yang

Tae-Hang Ahn

Heung-Jae Cho

Kwon Hong

Tae-Yoon Kim

Kwan-Yong Lim

Se-Aug Jang

Min-Gyu Sung

Seung-Ryong Lee

The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.

Semiconductor device and method for isolating the same

A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer.

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Semiconductor device with bulb-type recessed channel and method for fabricating the same

A method for fabricating a transistor, the method includes forming a gate over a substrate to form a first resultant structure, forming a gate spacer at first and second sidewalls of the gate, etching portions of the substrate proximate to the gate spacer to form a recess in a source/drain region of the substrate, forming a first epitaxial layer including germanium to fill the recess, and performing a high temperature oxidation process to form a second epitaxial layer including germanium over an interfacial layer between the substrate and the first epitaxial layer, the second epitaxial layer having a germanium concentration that is higher than a germanium concentration of the first epitaxial SiGe layer, thereby forming a second resultant structure.

Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; forming a capacitor insulation layer on the etch stop layer; forming an opening exposing the conductive region by selectively etching the capacitor insulation layer and the etch stop layer; growing a selective epitaxial growth (SEG) layer in the conductive region exposed through the opening; forming a metal layer for a capacitor bottom electrode along a profile provided with the opening; forming an isolated capacitor bottom electrode by removing the metal layer until the capacitor insulation layer is exposed; and removing the capacitor insulation layer, thereby making the capacitor bottom electrode have a cylinder type structure.

Method for forming semiconductor device capable of preventing bunker defect

The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.

Growing community of inventors

Ichon-shi, South Korea

Seung-Ho Pyi