Samsung Electronics Co., Ltd.

Lg Chem, Ltd

University of California

Woongjin Coway Co., Ltd

Seung-Heon Lee

Munjun Kim

In-Seok Hwang

Young-Jun Hong

ByeongJu Bae

Dong-wook Lee

Sang-Ki Chun

Young-Min Ko

Hong-gun Kim

Ji-Young Hwang

Ha-Young Yi

Ji-Eun Kim

Kyung-Ho Chae

Tae-Jong Han

Hyeon Sik Choi

Ki-Hwan Kim

Su-Jin Kim

Pierre M Petroff

Yoosang Hwang

Ji Young Hwang

Hyun-Woo Lee

Sunghee Han

Taejin Park

Se-Hoon Kim

Edward J Kramer

Jiehyun Seong

Eunkee Hong

Sohyun Park

Ik Soo Kim

Kyu-Tae Na

Byoung Deog Choi

Mansug Kang

Won-Hee Choe

Youn-seok Choi

Beom-Mo Koo

Mun-jun Kim

Min-Choon Park

Yong-Koo Son

Jaekang Koh

Chang-Gun Um

Kyung-Il Lee

Jie-Hyun Seong

Sang-hyuk Im

Frédéric S Diana

Antonio Badolato

Sung-Worl Jin

Ju-Wan Kim

Hyo-Sub Kim

Jin-Young Park

Inkyoung Heo

Tae-Sik Kang

Taek-Jung Kim

Jong Taik Lee

Honggun Kim

Soo Yeon Heo

Houng-Sik Yoo

Su Jong Kim

Kyoung Su Jeon

Yong-hyup Kim

Ji-Su Kim

Soon-Yeol Lee

Sang-Hyuk Im

Young-Sik Seo

Byeong Ju Bae

Jae-Young Jho

Soon-Yeel Lee

Do-Hyun Jin

Jong-Pyo Kim

Won-Yong Choi

Seo-Young Lee

Jee-Young Yeom

Han-Tak Kwak

A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

Methods of fabricating semiconductor device

A semiconductor memory device and associated methods, the device including first and second lower conductive lines extending in a first direction; a first middle conductive line on the first and second lower conductive lines and extending in a second direction; first and second memory cells between the first and second lower conductive lines and the first middle conductive line; an air gap support layer between the first and second memory cells; and a first air gap between the first and second memory cells and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as the first and second memory cells, the first and second memory cells include first and second OTS layers and first and second phase-change layers, and the first air gap overlaps the first and second phase-change layers.

Semiconductor memory device and method of fabricating the same

Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

Method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Semiconductor memory device having spacer capping pattern disposed between burried dielectic pattern and an air gap and method of fabricating same

A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.

Semiconductor device including a plurality of electrodes and supporters

A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.

Three-dimensional semiconductor memory device

A method for fabricating a semiconductor device includes forming a first mask pattern on a first film to extend in a first direction, forming a first spacer on either side wall of the first mask pattern, forming a second film to cover the first spacer and the first film, and forming a second mask pattern on the second film. The second mask pattern extends in a second direction different from the first direction. The method further includes forming a second spacer on either side wall of the second mask pattern, etching the first film using the first spacer and the second spacer as etch masks to form a contact pattern, and removing the first and second spacers to expose the contact pattern.

Method of fabricating semiconductor device

Growing community of inventors

Seoul, South Korea

Seung-Heon Lee