Skhynix Inc.

Seung Han Oak

Hyung Sik Won

Jun Phyo Lee

Choung Ki Song

Dong Uk Lee

Sang Hyun Ku

Kwang Myoung Rho

Woo Yeong Cho

A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Stacked integrated circuit

A circuit for sensing and amplifying a signal of a signal line includes a sensing voltage generation circuit including a sensing circuit, the sensing voltage generation circuit configured to generate a sensing voltage by sensing and amplifying a line input signal based on a bias voltage, and a bias voltage generation circuit including a replication circuit, the replication circuit having a structure identical to a structure of the sensing circuit and generating a replication voltage and the bias voltage generation circuit configured to generate the bias voltage by comparing the replication voltage with a logic threshold level.

Circuit for sensing and amplifying signal of signal line

An electronic device includes a test control circuit configured to generate test codes, configured to generate reference voltages voltage levels of which are adjusted responsive to the test codes, and configured to generate a test current the amount of which is adjusted responsive to the reference voltages and an internal voltage detection circuit configured to generate a detection signal for controlling the driving of an internal voltage by detecting the internal voltage responsive to the test current.

Electronic device related to detection of internal voltage

A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Semiconductor device with memory banks and sense amplifier arrays

A sense amplifier includes a latch type sense unit that detects a voltage difference between a bit line and a bit line bar and causes a voltage difference between a first latch output node and a second latch output node. The sense amplifier further includes a first latch connection unit that electrically connects the bit line to and disconnects the bit line from the first latch output node.

Sense amplifier and semiconductor memory apparatus using the sense amplifier

A nonvolatile memory device may include a cell array and a sense amplifier. The cell array may be coupled with a global bit line and a global word line, and is applied with a read voltage through the global bit line. The sense amplifier may generate an output signal based on a voltage level of a sensing node which is coupled with the cell array through the global word line, and control the voltage level of the sensing node.

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Gyeonggi-do, South Korea

Seung Han Oak