Skhynix Inc.

Sk Hynik Inc.

Korea Information Security Agency

Seung Gu Ji

Byeong Gyu Park

Hyung Min Lee

Duck Hoi Koo

Sung Kwan Hong

Young Ick Cho

Jun Rye Rho

Ik Sung Oh

Hyun Yeul Lee

Dae Sung Kim

Seok Jin Joo

Dong Jae Shin

Min Hwan Moon

Young Gyun Kim

Chung Un Na

In Ho Jung

Dae Seok Shin

Sung Hun Jeon

Dong Hwan Kim

Se Hwa Jang

Hyun Cheol Jeong

Mi Yeon Yoon

Yoo Jae Won

A suspend parameter determination device may include a power monitoring circuit configured to monitor power consumption information of a storage device; a memory device configured to store an artificial intelligence model; and a control circuit configured to load the artificial intelligence model, input to the artificial intelligence model, performance information for the storage device and the power consumption information received from the power monitoring circuit, and transmit, to the storage device, a suspend parameter outputted by the artificial intelligence model.

Suspend parameter determination device and method thereof

A storage device may determine a target memory block from among a plurality of memory blocks, determine a target memory unit from among the plurality of memory units included in the target memory block, and program target dummy data into the target memory unit when it is determined that the target dummy data is not programmed into the target memory unit and when the program operation for the target memory unit is not yet completed.

Storage device programming target dummy data in target memory unit and operating method of the storage device

A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Storage device and method for foggy and fine programming

A memory system comprises a memory device including a plurality of memory blocks, and a controller configured to manage a first count, a second count, and a sum value for each of the plurality of memory blocks, the first count being the number of performed random read operations, the second count being the number of performed sequential read operations, the sum value being calculated based on the first count and the second count, and configured to perform a read reclaim operation for a specific memory block among the plurality of memory blocks based on a comparison result of the sum value for the specific block with a reference value.

Memory controller for performing read reclaim operation, memory system including the same, and operating method of memory controller

Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. Based on embodiments of the disclosed technology, the memory system may suspend a target operation, which is a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. Accordingly, the memory system is capable of preventing a problem in that the end time of a program operation or an erase operation is excessively delayed, and controlling the number of times a program operation or an erase operation is suspended.

Memory system, memory controller, and operation method of memory system

A storage device having enhanced operating efficiency includes a memory device with a plurality of memory blocks and a memory controller that performs an operation of de-randomizing data stored in different memory blocks using an identical random seed. The memory controller includes a random table that has a first address group including physical page addresses of a first memory block and a second address group including physical page addresses of a second memory block. The random table also has a random seed group that includes random seeds corresponding to the first address group and the second address group.

Storage device for storing randomized data and operating method of the same

Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.

A controller includes: a command queue scheduler for queuing normal commands, and providing a priority order to a suspend command, when the suspend command is input; a data input/output component for outputting data in response to a data output signal output the command queue scheduler, and stopping the output of the data in response to a data output stop signal; and a data monitor for dividing data input to the data input/output component into a plurality of data groups, and monitoring information of a data group including data currently output from the data input/output component. The data input/output component outputs data up to the currently output data included in the data group and then stops the output of the data, in response to the data output stop signal. The command queue scheduler outputs the suspend command, when the output of the data group is stopped.

Controller and memory system having the same

A memory system includes a nonvolatile memory device; a random access memory configured to store, in response to an unmap request received from a host device, a flag information indicating that an unmap address as a target of the unmap request is unmapped; and a control unit configured to flush the flag information to the nonvolatile memory device, wherein the control unit flushes the flag information to the nonvolatile memory device when a first condition is satisfied.

Memory system using SRAM with flag information to identify unmapped addresses

A memory controller capable of controlling a memory device to perform a fine program operation, based on a time elapsing from a foggy program completion time and a position of a page on which a fine program is performed controls the memory device including a plurality of pages. The memory controller includes: a fine program timer for recording a foggy program completion time at which a foggy program completion response corresponding to a foggy program operation is received from the memory device, and outputting dummy program instruction information, based on an elapsing amount of time from the foggy program completion time; and a command controller for outputting a fine program command, based on the dummy program instruction information.

Memory controller and operating method thereof

A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.

Apparatus and method for recovering a data error in a memory system

A data storage device may include: a nonvolatile memory apparatus including a plurality of groups configured by dividing a plurality of planes in interleaving units; and a controller configured to check whether a group including a read region of a current read command is included in a group including a read operation of a previous read command and whether the read region of the current read command extends over two or more groups, when receiving the current read command, and control the nonvolatile memory apparatus to perform cache read or interleaving read based on the check result.

Data storage device with improved read performance and operating method thereof

A data storage device includes a nonvolatile memory device; and a controller suitable for setting a termination condition of a garbage collection operation based on an over-provisioning ratio of the nonvolatile memory device, performing the garbage collection operation, and terminating the garbage collection operation according to the termination condition.

Data storage device and operating method thereof for performing a garbage collection operation in consideration of a lifetime of a nonvolatile memory device

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Seoul, South Korea

Seung Gu Ji