Texas Instruments Corporation

Qualcomm Incorporated

International Business Machines Corporation

Sematech, Inc.

Seung-Chul Song

Mohamed Hassan Abu-Rahma

Beom-Mo Han

Brian Keith Kirkpatrick

Deborah J Riley

Chet Vernon Lenox

Seong-Ook Jung

Hyunkook Park

Hiroaki Niimi

Zhongze Wang

Lixin Ge

Prashant Majhi

Kisik Choi

Sei Seung Yoon

Amitabh Jain

James Walter Blatchford

Cheng Zhong

Anosh Bomi Davierwalla

Dongkyu Park

Kwan-Yong Lim

Byoung Hun Lee

Craig Henry Huffman

Joel Barnett

Rino Choi

Sang Ho Bae

Jong Hoan Sim

Zhibo Zhang

Byong Sun Ju

Mingu Kang

Mohamed Abu-Rahama

Anosh B Davierwalla

A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

Replacement metal gate process for CMOS integrated circuits

A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

Low-power 5T SRAM with improved stability and reduced bitcell size

Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

Stable SRAM bitcell design utilizing independent gate FinFET

An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

Inner L-spacer for replacement gate flow

An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile

An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.

Apparatus and method to fabricate an electronic device

An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.

Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved gate spacer control

A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.

Raised source/drain MOS transistor and method of forming the transistor with an implant spacer and an epitaxial spacer

Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile

A method includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel ('fin'), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.

Fin-type device system and method

A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.

Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor

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Austin, TX, United States of America

Seung-Chul Song