Electronics and Telecommunications Research Institute

Seung-Chul Lee

Min-Hyung Cho

Jong-Dae Kim

Mun-Yang Park

Kwi-Dong Kim

Gyu-Hyun Kim

Jong-Ki Kwon

Chong-Ki Kwon

There is provided a quadrature modulation transmitter which is capable of solving several problems of the conventional transmitter while performing the same function as the heterodyne transmitter or the digital IF transmitter, in which a circuit structure is simplified and a power consumption is reduced compared with the conventional transmitter. The quadrature modulation transmitter includes: a digital processing block for receiving an I-channel data, a Q-channel data and a clock signal, modulating the I-channel data or an inverted I-channel data into a first analog signal by means of an I-channel DAC according to a switching of an I-clock signal identical to the clock signal, and modulating the Q-channel data and an inverted Q-channel data into a second analog signal by means of a Q-channel DAC according to a switching of a Q-clock signal, the Q-clock signal being an inverted clock signal; and an analog processing block for receiving the first and second analog signals from the digital processing block, adding the first and second analog signals, converting the added signal into an RF domain signal through a mixing operation, and amplifying and transmitting the RF domain signal.

Quadrature modulation transmitter

A multiplying digital to analog converter comprising a digital to analog converter having a plurality of capacitors coupled in parallel, applying first signals to the capacitors during a sampling period, and applying second signals to the capacitors during an amplifying period, and an amplifier including a first amplifier electrically coupled to the digital to analog converter; a second amplifier electrically coupled to the first amplifier; and a first switch electrically coupled between an input end and an output end of the second amplifier, being turned off during a sampling period, and being turned off during an amplifying period.

Multiplying digital to analog converter and multipath pipe line analog to digital converter using the same

Disclosed is a current-steering digital-to-analog converter (DAC) which comprises a decoder for receiving an N-bit digital input signal and converting the same into first and second (N&#x2212;1)-bit digital signals, M (=2) current cells for supplying the current based on the two digital signals, a current cell driver for generating a first analog voltage and a second analog voltage corresponding to the currents based on the two (N&#x2212;1)-bit digital signals by control of a first clock signal and a second clock signal, and an amplifying circuit for sampling and holding the first and second analog voltage with reference to the first and second clock signals to generate a glitch-removed signal.

Current-steering digital-to-analog converter

Growing community of inventors

Daejeon, South Korea

Seung-Chul Lee