Electronics and Telecommunications Research Institute

Crystalgenomics, Inc.

Yuyu, Inc.

Seung Chul Lee

Kwi Dong Kim

Young Deuk Jeon

Jong Kee Kwon

Jong Dae Kim

Chong Ki Kwon

Min Hyung Cho

Kyung Soo Kim

Young Kyun Cho

Mun Yang Park

Joong Myung Cho

Jae Won Nam

Yi Gyeong Kim

Dongkyu Shin

Seonggu Ro

Tae Gyu Lee

Jin Hwan Kim

Gyu Hyun Kim

Young Ho Jeon

Young-Lan Hyun

Kyung Joo Lee

Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.

Method of algorithmic analog-to-digital conversion and algorithmic analog-to-digital converter

Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

Method of controlling pipeline analog-to-digital converter and pipeline analog-to-digital converter implementing the same

Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure. In a multiplying digital-to-analog converter (MDAC) used in the multi-bit pipeline ADC, switches are connected between the bottom plates of respective differential capacitors, thereby constantly maintaining a uniform input common mode voltage regardless of an input digital code. Thus, it is possible to improve the operating speed and performance of the MDAC.

Multi-bit pipeline analog-to-digital converter having merged capacitor switching structure

Provided is a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode. The ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; an n+1 number of B-bit flash ADCs for receiving an analog signal and converting the analog signal into a digital signal to output the digital signal; an n number of B-bit multiplying digital-to-analog converters (MDACs) for converting a difference between the digital signal output from the B-bit flash ADC and the front-stage output signal into an analog signal to output the analog signal to the next stage; and a mode control circuit for generating n-bit control signals to control the B-bit flash ADC and the B-bit MDAC according to required resolution and operating frequency. In the multi-bit pipeline ADC, an operating mode is altered by controlling the number of stages in a pipeline and a signal path according to required resolution and operating frequency, so that power consumption can be minimized under the corresponding operating condition and signals can be processed in a variety of ways.

Multi-bit pipeline analog-to-digital converter capable of altering operating mode

Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.

Algorithm analog-to-digital converter

A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N&#x3e;= and K&#x3e;=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size. In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.

Multi-bit pipeline analog-to-digital converter having shared amplifier structure

A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.

Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor

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Provided is a pipelined folding analog-digital converter, the pipelined folding analog-digital converter comprising: a first sample-and-hold unit that samples and outputs a number of analog input voltages; a reference voltage generator that generates a number of reference voltages; a pre-amplifier that amplifies and outputs a number of values subtracting each reference voltage from the outputs of the first sample-and-hold unit, wherein an offset effect due to asymmetry of the amplifier is eliminated; a first folder that folds and outputs a number of outputs of the pre-amplifier; a second sample-and-hold unit that samples and outputs a number of outputs of the first folder; a second folder that folds and outputs a number of outputs of the second sample-and-hold unit; and a comparator that performs a comparison operation between the outputs of the pre-amplifier and the output values of the second folder to find a digital output value, whereby the offset caused by the device mismatch is removed, so that it is possible to realize a high-resolution analog-digital converter.

Analog-digital converter with pipeline folding scheme

The present invention relates to a current cell driving circuit in a digital-to-analog converter. The current cell driving circuit limits the potential of differential control signals to a given potential level by means of a voltage limiter using a parasitic capacitance of a transistor. Therefore, the present invention can effectively limit the potential of differential control signals DP and DN without compromising the power consumption and the circuit area and also can minimize the transfer time.

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Daejeon, South Korea

Seung Chul Lee