Samsung Electronics Co., Ltd.

Seung-Cheol Oh

Hi-Choon Lee

Yong-Sik Seok

Moon-Gone Kim

A synchronous memory includes a column main-decoder circuit that is directly coupled to column select lines (CSL), and a timing controller that controls both enable timing and disable timing of the column select lines by controlling the column pre-decoder. The CSL timing controller generates a CSL timing control signal representative of the enable timing and the disable timing of the column select lines. The column pre-decoder is either enabled or disabled depending upon logic states of the CSL timing control signal. The timing controller includes a first control circuit which provides a CSL enable control signal, a CSL disable control circuit which provides a CSL disable control signal, and a flip-flop circuit which receives the CSL enable and disable control signals and provides the CSL timing control signal.

Column select line control circuit for synchronous semiconductor memory

A dynamic column redundancy driving circuit for a synchronous semiconductor memory device is provided. The circuit includes a first node, a precharging portion, an address determining portion, a clock delay portion, and a driving portion. The precharging portion precharges the first node in the first phase of the clock. The address determining portion is connected to the first node and includes a plurality of fuses selectively disconnected according to a defect address and changes a logic level of the first node in the second phase of the clock according to whether an address matches the defect address. The clock delay portion delays the clock. The driving portion receives the output of the address determining portion and the output of the clock delay portion and produces a redundancy wordline driving signal.

Dynamic column redundancy driving circuit for synchronous semiconductor

A voltage detecting circuit and method in a synchronous DRAM is disclosed. The circuit includes first and second pull-up switching portion, first and second pull-down switching portion, first and second pull-up portion, first and second pull-down portion, ; switching transistor and a driving portion. The pull-up and pull-down switching portion are selectively turned-on according to a mode control signal, and the current paths are different for the active power down mode and the normal mode. Each pull-up portion includes a plurality of NMOS transistors connected in series and gated by the boosted voltage and each pull-down portion includes a plurality of NMOS transistors connected in series. An effective channel length of the current path selected in case of the active power down mode is longer than that selected in case of the normal operation mode. Accordingly, the resistance of the pull-up portion and the pull-down portion in the active power down mode increases to thereby reduce the current flow and power consumption.

Voltage detecting circuit and method for reduced power consumption

A row redundancy circuit for use in a semiconductor memory device having one memory cell array, and first and second main row decoders and first and second spare row decoders formed on both sides of the memory cell array includes a first fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the first spare row decoder, a second fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the second spare row decoder, and a row redundancy control circuit for receiving the output signals of the first and second fuse boxes and selectively supplying an output signal responsive to the received input signal level to the first and second spare row decoders.

Row redundancy circuit and method for a semiconductor memory device with

A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.

Circuit for controlling isolation transistors in a semiconductor memory

Disclosed is a semiconductor device with redundancy for replacing a memory cell with a predetermined defect with additional spare cells. In a semiconductor memory device having a plurality of normal submemory arrays, the present invention discloses a redundancy technique that allows any redundant address decoder to be used with any of the submemory arrays. This maximizes efficiency in redundant repairs as well as maximizes the use of the chip area.

Growing community of inventors

Suwon, South Korea

Seung-Cheol Oh