Lg Display Co., Ltd.

Seung-Chan Choi

Yong-Ho Jang

Jung-eun Lee

Jae-Kyun Lee

Moo-Hyoung Song

Jae-Yong You

Jeong-Oh Kim

Woo-Seok Choi

Jei-Hyun Lee

Binn Kim

Nam-Wook Cho

Woo-seok Choi

Min-Doo Chun

A display apparatus having a connection electrode which crosses a bending area may be provided. The connection electrode may be disposed on a device substrate including a bending area between a display area and a pad area. The connection electrode may connect the display area and the pad area across the bending area. The connection electrode may have a stacked structure of the lower connecting electrode and the upper connecting electrode. A light-emitting device, an encapsulating element and a touch electrode may be sequentially stacked on the display area of the device substrate. The upper connecting electrode may include the same material as the touch electrode. Thus, in the display apparatus, the disconnection of the connection electrode due to bending stress and external impact may be reduced.

Display apparatus having a connecting electrode which crosses a bending area

Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Shift register

A data driving apparatus and method for a liquid crystal display (LCD) device is provided, the apparatus including: a liquid crystal panel; a timing controller configured to output control signals for controlling the driving of a gate driving unit and a data driving unit; a gate driving unit configured to output a gate on signal to gate lines of the liquid crystal panel; a data driving unit configured to drive data lines of the liquid crystal panel, the data driving unit providing an overdriving signal to at least one of a pair of pixel signals of the same polarity applied to adjacent data lines for supply to longitudinally adjacent pixels of the liquid crystal panel, and wherein the data driving unit drives the liquid crystal panel according to a longitudinal two-dot inversion polarity pattern.

Data driving apparatus and method for liquid crystal display device

A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.

Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.

A gate driving circuit includes a first clock generator to output n output control clock pulses having different phases; a second clock generator to create m*n output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register sequentially outputting a plurality of scan pulses.

Gate driving circuit

Disclosed herein is a gate driving circuit including a first clock generator to sequentially output n output clock pulses, a second clock generator to sequentially output n output control clock pulses, and a shift register to receive the n output clock pulses and the n output control clock pulses and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th output clock pulses output during adjacent periods overlap with one another, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k&#x2212;a)-th output clock pulse, a high section of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th output clock pulse falls during the high section of the output control clock pulses not overlapping with that of the k-th output clock pulse.

An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

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Goyang-si, South Korea

Seung-Chan Choi