Hynix Semiconductor Inc.

Seung-Bum Kim

Jung-Taik Cheong

Dong-Sauk Kim

Ki-Won Nam

Ky-Hyun Han

Jae-Young Kim

A method for patterning a metal line includes forming a barrier metal layer and a metal layer, etching the metal layer, etching the barrier metal layer to form a passivation layer on an etched surface of the barrier metal layer, and cleaning a resultant structure where the passivation layer is formed.

Method for patterning metal line in semiconductor device

A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a first recess having a bottom middle portion roundly projected and bottom edge portions tapered to have a micro-trench profile; and etching the substrate beneath the first recess to form a second recess, the second recess being rounded and being wider than the first recess.

Method for fabricating semiconductor device

A method for fabricating a recess gate in a semiconductor device is provided. The method includes selectively etching an active region of a substrate to form a recess pattern, performing a post treatment on the recess pattern using a plasma, and forming a gate pattern in the recess pattern.

Method for fabricating a recess gate in a semiconductor device

The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Semiconductor memory device and method for fabricating the same

A method for fabricating a semiconductor device with a step gated asymmetric recess is provided. The method includes: forming an organic bottom anti-reflective coating (BARC) layer over a substrate; forming a patterned mask over the organic BARC layer that expose selected portions of the organic BARC layer; etching the exposed portions of the organic BARC layer using an etch gas with high selectivity to the substrate until the substrate underlying the exposed portions of the organic BARC layer is substantially exposed; etching the exposed portions of the substrate to form a plurality of recessed active regions; removing the mask and the organic BARC layer to expose a plurality of protruding active regions defined by the recessed active regions; forming a gate insulation layer over the recessed active regions and the protruding active regions; and forming asymmetric step-structured gates over the gate insulation layer, each gate extending over the corresponding recessed active region and the corresponding protruding active region.

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Ichon-shi, South Korea

Seung-Bum Kim