Texas Instruments Corporation

Seung Bae Lee

Srinath Mathur Ramaswamy

Ajit Sharma

Arup Polley

Sriram Narayanan

Scott Robert Summerfelt

Wei-Yan Shih

Terry Lee Sculley

Alok Kumar Lohia

Steve Kummerl

Mark Stephen Toth

Sudhir Nagaraj

Michael Edwin Butenhoff

Wen Li

An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.

Piezoelectric sensor apparatus

Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.

Transconductance shifted differential difference amplifier

An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element may include a conditioning circuit, temperature gauge, FRAM and a processor core.

Integrated force sensing element

The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.

Optical receiver chain for components of a photoplethysmograph signal

Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.

Methods and apparatus for reducing noise, power and settling time in multi-modal analog multiplexed data acquisition systems

A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) is calibrated by determining an error voltage for each of a plurality of most significant bit (MSB) capacitors in a first segment using a calibration DAC. The first segment is connected to the second segment by an attenuation capacitor. Each of the error voltages corresponding to the MSB capacitors is digitized to form a set of digitized error voltages. An error voltage for each of a plurality of less significant bit (LSB) capacitors in at least the second segment is calculated by summing the set of digitized error voltages to form a sum of error voltages (sum(e)) and assigning a percentage of sum(e) as the error voltage for each of the LSB capacitors, such that a mismatch in the attenuation capacitor is mitigated.

Mismatch correction of attenuation capacitor in a successive approximation register analog to digital converter

The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) () is substantially reduced by using a number of shared capacitors (SC-SCs&#x2212;1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.

Calibrated SAR ADC having a reduced size

An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.

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Allen, TX, United States of America

Seung Bae Lee