Samsung Electronics Co., Ltd.

Seulgi Yun

Juyoun Kim

Seki Hong

Sangjung Kang

Jinwoo Kim

Hyung Jong Lee

Junmo Park

Jihwan An

Myungsoo Seo

A semiconductor device includes a substrate having a first, a second, a third, and a fourth region; a first gate structure in the first region and including a first gate dielectric layer, and a first, a second, and a third conductive layer; a second gate structure in the second region and including a second gate dielectric layer, and the second and the third conductive layer; a third gate structure in the third region and including a third gate dielectric layer, and the second and the third conductive layer; and a fourth gate structure in the fourth region and including the second gate dielectric layer, and a fourth and the third conductive layer. The first gate dielectric layer includes a material of the second gate dielectric layer and a first element, and the third gate dielectric layer includes a material of the second gate dielectric layer and a second element.

Semiconductor devices

A semiconductor device includes a first active pattern on a substrate. The first active pattern includes a pair of first source/drain patterns and a first channel pattern therebetween. A gate electrode is disposed on the first channel pattern, and a first gate spacer is disposed on a side surface of the gate electrode. The first gate spacer includes a first spacer and a second spacer. A top surface of the first spacer is lower than a top surface of the second spacer. A first blocking pattern is disposed on the first spacer, and a gate contact is coupled to the gate electrode. The first blocking pattern is interposed between the gate contact and the second spacer.

Semiconductor device and method of fabricating the same

A method of manufacturing a semiconductor device includes forming a dummy gate structure on a substrate, partially removing the dummy gate structure to form a first opening that divides the dummy gate structure, forming a first division pattern structure in the first opening, replacing the dummy gate structure with a gate structure, removing the first division pattern structure to form a second opening, removing a portion of the gate structure from a sidewall of the second opening to enlarge the second opening, and forming a second division pattern in the enlarged second opening.

Semiconductor device with gate electrode with flat upper surface and no protruding portion and methods of manufacturing the same

A semiconductor memory device includes a substrate having a first region and a second region. A first gate electrode layer is on the first region and includes a first conductive layer including a first plurality of layers, and includes a first upper conductive layer on the first conductive layer. A second gate electrode layer is on the second region and includes a second conductive layer including a second plurality of layers, and includes a second upper conductive layer on the second conductive layer. At least one of the first plurality of layers includes titanium oxynitride (TiON). A first transistor including the first gate electrode layer and a second transistor including the second gate electrode layer are metal oxide semiconductor field effect transistors (MOSFETs) having the same channel conductivity type, and a threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes first and second transistors on a substrate. The first transistor includes a first N-type active region, a first gate electrode having a first work function layer, and a first gate dielectric layer having high-k dielectrics containing La. The first work function layer includes a first layer having TiON, a second layer having TiN or TiON, a third layer having TiON, a fourth layer having TiN, and a fifth layer having TiAlC. The second transistor includes a first P-type active region, a second gate electrode having a second work function layer, and a second gate dielectric layer having high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer.

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Hwaseong-si, South Korea

Seulgi Yun