Samsung Electronics Co., Ltd.

Skhynix Inc.

Seoul National University

Seuk Son

Jaehyun Park

Hyeonju Lee

Kangjik Kim

Nakwon Lee

Sunggeun Kim

Jiyoung Kim

Hobin Song

Juyun Lee

Youngjun Kim

Jaeha Kim

Hanseok Kim

Kyeongjoon Ko

Seungheon Baek

Sooeun Lee

Dongchul Choi

Byunghyun Lim

A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

Clock data recovery circuit and apparatus including the same

A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.

Digital loop filter of low latency and low operation and clock data recovery circuit including the same

A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

Semiconductor device

A phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates first and second thermometer codes and a selection signal based on a code. The DAC includes unit cells, determines two of weight signals as first and second target weight signals based on the selection signal, and adjusts a current of the first and second target weight signals by controlling the unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of input clock signals as first and second target clock signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The unit cells include different first and second unit cells.

Monotonic and glitch-free phase interpolator and communication device including the same

An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.

Pattern generator and built-in-self test device including the same

A circuit module includes a model circuit and a look-up table (LUT). The model circuit generates an output signal based on one or more input signals, and corresponds to a digital circuit. The LUT stores one or more control signals and one or more operation parameters that are to be used to implement the model circuit. The one or more control signals and the one or more operation parameters correspond to an index determined by a combination of the one or more input signals and the output signal.

Circuit module for modelling a digital circuit and simulation device including the circuit module

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Seoul, South Korea

Seuk Son