Texas Instruments Corporation

Seuk B Kim

Tpinn R Koh

Douglas Edward Wente

T-Pinn Koh

Apparatus and methods are presented for using configurable additive data scrambling or descrambling circuitry for multichannel link aggregators in which a scrambler or descrambler polynomial is specified by binary data in a programmable register, and the polynomial data is used to compute a polynomial matrix. A scrambler or descrambler pattern is computed according to the polynomial matrix, and input data is bitwise exclusive-ORed with the computed scrambler or descrambler pattern to generate scrambled or descrambled output data. The scrambling or descrambling circuitry can be reconfigured for different polynomials by reprogramming the register, with the scrambler or descrambler automatically computing an updated polynomial matrix.

Link aggregator with universal packet scrambler apparatus and method

An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

Flexible PRBS architecture for a transceiver

An apparatus is provided. A polynomial register having a plurality of bits is provided, where the polynomial register is configured to store a user-defined polynomial. A transceiver is coupled to a first bus, a second bus, and the polynomial register. The transceiver includes a self-synchronous scrambler that is configured to generate a scrambled signal from a first signal using the user-defined polynomial and a self-synchronous descrambler that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

Flexible scrambler/descrambler architecture for a transceiver

A method for encoding data words into a frame is provided. Input data words are received on a first bus having a first width. The input data words are buffered so as to output intermediate data words onto a second bus having a second width. A transcode bit is generated from the intermediate data words, and a set of parity bits is generated from the intermediate words using a syndrome generator, where the syndrome generator uses a number of bits that are equal to the second width. A frame is then generated from the intermediate data words and the set of parity bits and is output to a third bus having the first width.

Forward error correction encoder

A method for determining an initial alignment for a frame of input data is provided. A frame for the input data is set, and the frame is synchronized. Specifically, a syndrome check of the frame is performed using a first predetermined number of bits, and a slip of a second predetermined number of bits is requested following the syndrome check. Evaluation of the syndrome check to determine whether the frame is aligned can then be performed in parallel with the slipping. The evaluation and slipping can then be repeated if the frame is misaligned. When the frame is aligned, a lock condition can be indicated, and the slip performed in parallel with the evaluation indicating that the frame is aligned can be deasserted. In addition, when the frame is aligned, error correction on the frame can be performed, and the error corrected frame can be formatted.

Growing community of inventors

Plano, TX, United States of America

Seuk B Kim