Ay Dee Kay LLC

Setu Mohta

Scott David Kee

Christopher A Menkus

David Kang

Aravind Loke

An integrated circuit that includes an analog frequency-selective gain filter having a frequency-selective gain corresponding to a high-pass filter prior to an analog-to-digital converter (ADC) is described. During operation, the analog frequency-selective gain filter may provide frequency-selective gain (such as a high-pass filter characteristic) to an electrical signal corresponding to a received signal (such as a LiDAR signal, a sonar signal, an ultrasound signal and/or a radar signal) in a ranging receiver. Note that the received signal may correspond to a received frequency-modulated continuous-wave (FMCW) signal. Moreover, the integrated circuit may include a digital processing circuit after the ADC and control logic that instructs the digital processing circuit to characterize the frequency-selective gain (such as an amplitude and/or a phase at a frequency) during a calibration mode. Furthermore, the digital processing circuit may correct an output signal from the ADC based at least in part on the characterized frequency-selective gain.

Frequency-selective compensation in ranging receivers utilizing chirped waveforms

An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Configuration of ADC data rates across multiple physical channels

Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.

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Aliso Viejo, CA, United States of America

Setu Mohta