Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Microcomputer System, Ltd.

Hitachi Computer Engineering Co., Ltd.

Hitachi Tobu Semiconductor

Hitachi Communication Systems, Inc.

Hitachi Microcomputer Eng. Ltd.

Hitachi Microcomputer

Setsuo Ogura

Makoto Furihata

Shizuo Kondo

Yukinori Kitamura

Kazuyuki Kamegaki

Kouichi Yamazaki

Eiji Minamimura

Takahiro Okabe

Shuzo Nagumo

Makoto Hayashi

Katsuyoshi Washio

Tomoyuki Watanabe

Yuji Kobayashi

Masumi Kasahara

Osamu Takada

Minoru Nagata

Kenji Kaneko

Toshinori Hirashima

Shunji Mori

Mitsuya Sato

Kenya Yamauchi

Shiro Mayuzumi

Tuyoshi Nagase

Katuhiro Morisuye

Hideo Miyazaki

Shirou Mayuzumi

Akira Takigawa

Mikio Haijima

Yoshiki Akamatsu

Toshiyuki Fukamachi

When a semiconductor integrated circuit device having a wiring structure of three or more layers is hierarchically considered as a collection of a plurality of functional blocks, each functional block is internally connected by wirings in the first wiring layer, in which wirings have their main extended direction prescribed to be the X-direction, and wirings in the second wiring layer, in which wirings have their main extended direction prescribed to be the Y-direction, formed over the first wiring layer. Wirings in the third wiring layer, in which wirings have their main extended direction prescribed to be the same as the wirings in the second wiring layer, formed over the second wiring layer, together with wirings in the first and second wiring layer, are used as signal wirings between functional blocks, while the wirings in the third wiring layer are used as power supply wirings for providing power supply to functional blocks. As the power supply paths to functional blocks, a plurality of power supply wirings are branched off from the power supply electrode such as a power supply pad and terminated there. The power supply electrode on the high voltage side and the power supply electrode on the low voltage side are disposed separately at opposing edge portions of the semiconductor substrate and the power supply wirings proceeding therefrom to their target functional blocks are bent in the vicinity of the edge portion of the semiconductor substrate and therefrom extended straight to the target points.

Semiconductor integrated circuit device

Disclosed is a novel semiconductor integrated circuit device for use in a color VTR (Video Tape Recorder). Concretely, the semiconductor integrated circuit device comprises a substantially rectangular semiconductor chip which has a principal surface, a luminance signal processing unit and a color signal processing unit which are disposed at the positions of the principal surface opposing to each other, and a semiconductor region which is provided in the interspace of the principal surface between the luminance signal and color signal processing units opposing to each other and which is supplied with a bias stable A.C.-wise. Further, the semiconductor region is located substantially at the central portion of the semiconductor chip and is extended so as to intersect with one set of opposing sides of the rectangular semiconductor chip.

Herein disclosed is a semiconductor device including a plurality of IIL elements which are electrically connected by a plurality of first wirings arranged generally parallel with one another and a plurality of second wirings arranged generally parallel with one another and extended in different direction to the first wirings.

Semiconductor device

A resistor is provided with a plurality of turn parts whose corners have an obtuse flexional angle in order to improve the relative resistance precision. A ladder resistor can be formed with a plurality of such resistors connected in series, and various electronic devices are formed employing the ladder resistor.

Resistor and electron device employing the same

An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.

Bi-MOS PLA

A logic circuit is provided which includes a first multi-emitter transistor with its emitters coupled to a group of first input lines and a first transistor with its base coupled to the collector of said first multi-emitter transistor. A second transistor is also provided with its base coupled to the collector of said first transistor, said second transistor having a polarity opposite to that of said first multi-emitter transistor. A second multi-emitter transistor is connected with its base coupled to the collector of said second transistor and with its emitters coupled to a group of second input lines, and a third transistor is connected with its base coupled to the collector of said second multi-emitter transistor and with its collector coupled to an output line. The collector of said first multi-emitter transistor is coupled to the emitter of said second multi-emitter transistor in order to absorb minority carriers stored in the transistors. This feature significantly improves the circuit operating speed. A further feature is the provision of a logic circuit which is highly integrated and which consumes reduced amounts of electric power, while maintaining high-speed performance of the TTL circuit, by substituting a multi-collector transistor that reversely operates for an inverter portion of the TTL circuit.

Bipolar logic circuit having two multi-emitter transistors with an

A logic circuit of a large scale which consumes small amounts of electric power is comprised of a plurality of ROM portions each formed of IIL circuits. Input signal lines are commonly used to transmit input signals to the ROM portions. The plurality of ROM portions are selectively operated by ROM select signals, and outputs corresponding to the input signals are obtained from a selected ROM portion. To select a particular ROM portion out of the plurality of ROM portions, the emitters of inverse npn transistors of IIL circuits constituting the selected ROM portion are rendered to assume ground potential. In the meantime, the emitters of the inverse npn transistors of IIL circuits in the non-selected ROM portions are held in a floating condition. This makes it possible to obtain a logic circuit which consumes small amounts of electric power with a very simple construction since the non-selected ROM portions consume no power.

Logic circuit

An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array. The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate in the forward direction by a plurality of input signals, and a plurality of Schottky barrier diodes provided between the collectors of the bipolar transistors and output signal lines. The NOR or OR gate array includes a plurality of other bipolar transistors which are driven to operate in the backward direction by a plurality of output signals from the NAND or AND gate array.

PLA with forward-conduction bipolar 'and' array and I.sup.2 L 'OR' array

A semiconductor integrated circuit includes low voltage operation circuitries such as I.sup.2 L and high voltage operation circuitries operating at a higher voltage than the low voltage operation circuitries. Both of the low and high voltage operation circuitries are implemented in a single semiconductor chip in coexistence with each other. The low voltage operation circuitries are disposed in constant current paths in the high voltage operation circuitries so that the currents once used by the high voltage operation circuits are utilized again by the low voltage operation circuitries. Power dissipation of the whole integrated circuit is thus reduced significantly.

I.sup.2 L circuitry having operating current supplied by higher-voltage

A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

Semiconductor device having a junction capacitance, an integrated

Method of fabricating a semiconductor device utilizing simultaneous

Growing community of inventors

Takasaki, Japan

Setsuo Ogura