Fujitsu Corporation

Setsuo Kurafuji

Keizo Aoyama

Hideo Itoh

Kazuo Tanimoto

A semiconductor memory device having data buses for connecting memory cells in memory cell arrays with input/output buffer circuit includes a plurality of memory cell arrays having repetitive patterns. In the device, a plurality of column decoders are adjacent to the memory cell arrays and have repetitive patterns. A portion of the column decoders is displaced from a regular location in the column decoder to a separate location on a substrate of the semiconductor memory device to leave a blank portion in the column decoder. The device also includes an input/output buffer circuit, data buses for connecting the memory cell arrays to the corresponding input/output buffer circuit through spaces outside the column decoders including the blank portion, and conductors for connecting the displaced portion of column decoders located in the separate location to the corresponding memory cell arrays through spaces outside the column decoders including the blank portion.

Semiconductor memory device

A semiconductor device for use in a sense amplifier of a memory circuit includes a first load, a second load, third loads and first and second enhancement-type transistors. The first enhancement-type transistor is connected between the first load and the third loads and receives a data signal. The second enhancement-type transistor is connected between the second load and the third loads and receives a reference voltage. The reference voltage is compensated for by a temperature-compensating circuit so that the reference voltage is changed in accordance with a change in temperature.

Semiconductor device for use in a sense amplifier

A static RAM, including a bit-line-charging transistor connected, in parallel to the load transistor, between each bit line and the power supply. These bit-line-charging transistors are controlled by a control signal generator circuit, which provides a timed pulse to their gates at the conclusion of each write cycle. The width of this timed pulse is selected such that bit lines which have been driven to a low level (e.g., zero volts) during a write cycle are rapidly recharged to the low level (e.g., 2.5 volts) to which they might have been driven during a read cycle. Thus, reverse readout operations (e.g., where a '1' is read immediately after a '0' has been written) no longer pose an obstacle to improving read operation speed, and speed and density can be improved.

Static RAM with bit-line-charging transistor

In a decoder circuit in which a transistor for reducing power use, which is supplied at its gate with a first control signal, is connected in series with a logical gate composed of a load transistor and a plurality of transistors which are respectively supplied at their gates with address signals, there is provided an off buffer circuit which comprises a first inverter for receiving the output of the logical gate and a second inverter for receiving the output of the first inverter. To a load transistor of the second inverter is provided a second control signal delayed in phase behind the first control signal and the output of the off buffer circuit is used as a decoded output of the address signal, so that the rise and fall of a word line is reduced.

MOS Decoder circuit using phase clocking for reducing the power

A static memory circuit incorporating memory cells of a MOS static type comprising a plurality of potential setting circuits for setting the ground side potential of one selected memory cell to be lower than those of other non-selected memory cells. Thus, reducing power dissipation by reducing current flowing through half-selected and non-selected memory cells without reducing read speed.

Static memory circuit

A static type semiconductor RAM device comprising a latch circuit at every column which detects, amplifies and temporarily memorizes a read-out signal from each of the memory cells in the corresponding column and which has a large drive capacity. In the static type RAM device according to the present invention, each of the memory cells is used as an element which only holds information, and data bus lines are driven by the latch circuits having a large drive capacity, so that the slow down of the read-out speed and the decrease of reliability of read-out data of the static type RAM device having a large memory capacity is prevented.

Semiconductor RAM device

A substrate bias-voltage generator is comprised of an oscillator, and a charge pumping circuit, driven by the oscillator via a coupling capacitor, which transfers accumulated electric charges, out of the semiconductor substrate. The oscillator frequency is varied in accordance with the variation of the voltage level of the semiconductor substrate, preferably by means of an RC circuit, fabricated by a MOSFET variable resistance (R) and a capacitor (C), within a ring oscillator or a multi-vibrator. The gate electrode of the MOSFET variable resistance is directly connected to the semiconductor substrate.

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Yokohama, Japan

Setsuo Kurafuji