Mitsubishi Denki Kabushiki Kaisha

Setsu Kondo

Shigeki Ohbayashi

Takashi Hayasaka

Toshihiko Hirose

Masayuki Iketani

Yoshiyuki Fujino

A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

Static semiconductor memory device having improved characteristics

Semiconductor memory device operable to write data accurately at high

Static semiconductor memory device having circuitry for lowering

Static semiconductor memory device having circuitry for enlarging write

A semiconductor memory device has a plurality of memory cells arranged in rows and columns, a plurality of pairs of complementary first and second bit lines arranged corresponding to respective columns and connecting memory cells on a corresponding column, first and second read data lines, and a plurality of pairs of first and second bipolar transistor provided for respective pairs of first and second bit lines. Each first bipolar transistor is coupled to the first read data line and each second bipolar transistor is coupled to the second read data line and a plurality of first switching circuits transfer potentials of the first and second bit lines to respective bases of corresponding first and second bipolar transistors. A reference line transmits a non-selection level voltage and a plurality of second switching circuits, operating complementary to the corresponding first switching circuits, transfer the non-selection level voltage to bases of corresponding first and second bipolar transistors. Generator circuitry generates non-selection level voltage having (i) a potential level lower than or equal to a low level potential of a selected bit line in a data reading operation mode and (ii) a potential level higher than or equal to a high level potential of the selected bit line in an operation mode other than the data reading operation mode.

Semiconductor memory device having non-selecting level generation

Growing community of inventors

Hyogo, Japan

Setsu Kondo