Lsi Logic Corporation

Other

Cypress Semiconductor Corporation

Sethuraman Lakshminarayanan

Sey-Shing Sun

Vladimir Zubkov

Chuan-Cheng Cheng

Ravindra Manohar Kapre

Peter J Wright

Myongseob Kim

Hong Ying

Hao Cui

William K Barth

Agajan Suvkhanov

Grace S Sun

A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.

Memory structure having SRAM cells and SONOS devices

A method of forming a semiconductor structure includes rapid thermal annealing of a gate stack on a semiconductor substrate at a temperature of at least 950&#xb0; C., followed by forming source/drain regions in the semiconductor substrate.

Polycrystalline silicon activation RTA

A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.

Method for creating barrier layers for copper diffusion

Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

Low resistance metal interconnect lines and a process for fabricating them

Growing community of inventors

San Jose, CA, United States of America

Sethuraman Lakshminarayanan