International Business Machines Corporation

Seth L Knupp

Son Van Nguyen

Alfred Grill

Hosadurga K Shobha

Vamsi Krishna Paruchuri

Chih-Chao Yang

Daniel C Edelstein

Takeshi Nogami

Deepika Priyadarshini

Hong He

Marc Adam Bergendahl

Sean Teehan

James J Demarest

Raghavasimhan Sreenivasan

Allan Ward Upham

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Ultrathin multilayer metal alloy liner for nano Cu interconnects

A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth.

Epitaxially grown quantum well finFETs for enhanced pFET performance

Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

Multilayer dielectric structures for semiconductor nano-devices

Growing community of inventors

Schenectady, NY, United States of America

Seth L Knupp