Intel Corporation

Seth H Pugsley

Christopher B Wilkerson

Shih-Lien L Lu

Zeshan A Chishti

Kingsum Chow

Berkin Akin

Peng-Fei Chuang

Robert L Scott

Alaa R Alameldeen

Zhe Wang

Aamer Jaleel

Deborah T Marr

Jonathan Cannon Hall

Ganesh Venkatesh

Roger Gramunt

Chunhui Zhang

Manjunath Shevgoor

Mark Dechene

Khun Ban

Prabhat Jain

System configurations and techniques for implementation of a neural network in neuromorphic hardware with use of external memory resources are described herein. In an example, a system for processing spiking neural network operations includes: a plurality of neural processor clusters to maintain neurons of the neural network, with the clusters including circuitry to determine respective states of the neurons and internal memory to store the respective states of the neurons; and a plurality of axon processors to process synapse data of synapses in the neural network, with the processors including circuitry to retrieve synapse data of respective synapses from external memory, evaluate the synapse data based on a received spike message, and propagate another spike message to another neuron based on the synapse data. Further details for use and access of the external memory and processing configurations for such neural network operations are also disclosed.

Spiking neural network accelerator using external memory

Systems and techniques for neuromorphic accelerator multitasking are described herein. A neuron address translation unit (NATU) may receive a spike message. Here, the spike message includes a physical neuron identifier (PNID) of a neuron causing the spike. The NATU may then translate the PNID into a network identifier (NID) and a local neuron identifier (LNID). The NATU locates synapse data based on the NID and communicates the synapse data and the LNID to an axon processor.

Neuromorphic accelerator multitasking

Systems, apparatuses and methods may provide for a chip that includes a memory array having a plurality of rows corresponding to neurons in a spiking neural network (SNN) and a row decoder coupled to the memory array, wherein the row decoder activates a row in the memory array in response to a pre-synaptic spike in a neuron associated with the row. Additionally, the chip may include a sense amplifier coupled to the memory array, wherein the sense amplifier determines post-synaptic information corresponding to the activated row. In one example, the chip includes a processor to determine a state of a plurality of neurons in the SNN based at least in part on the post-synaptic information and conduct a memory array update, via the sense amplifier, of one or more synaptic weights in the memory array based on the state of the plurality of neurons.

In-memory spiking neural networks for memory array architectures

In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.

Method and system for coordinating baseline and secondary prefetchers

A processor may include a programmable memory prefetcher that includes a programmable hardware prefetch engine and a prefetch engine control register. The programmable memory prefetcher may include circuitry and may be configured to receive, during execution of an application, a first instruction for configuring the prefetch engine for prefetching multiple cache lines to be accessed in the future, at predictable locations, by the application; to store, in the prefetch engine control register, dependent on information in the first instruction, data representing an amount of prefetching to be performed, and data representing a stride distance between consecutive cache lines to be prefetched; to receive a second instruction for prefetching a single cache line whose location is identified in the second instruction; and to initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the prefetch engine, to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register. The prefetch engine control register may store multiple entries, each including an identifier of a given operation to prefetch multiple cache lines. An instruction may also be received to disable prefetching of multiple cache lines. The multiple cache lines may be prefetched from a last-level cache (LLC) to a mid-level cache.

Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register

In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.

Processor prefetch throttling based on short streams

An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.

Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory

A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.

Method and apparatus for pre-fetching data in a system having a multi-level system memory

A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

Instruction and logic for run-time evaluation of multiple prefetchers

A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.

System and method for cache replacement using conservative set dueling

In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

Growing community of inventors

Salt Lake City, UT, United States of America

Seth H Pugsley