Micron Technology Incorporated

Seth A Eichmeyer

Christopher Gordon Wieduwilt

James S Rehmeyer

Patrick J Mullarkey

Matthew D Jenkinson

Dean D Gans

George B Raad

Jason M Johnson

Victor Wong

William F Jones

Aron T Lunde

Benjamin Johnson

Tim Cowles

Kenji Yoshida

Matthew Alan Prather

Dmitry A Vengertsev

Nicola Ciocchini

John Christopher M Sancon

Jing Gong

Tom Tangelder

Yutao Gong

Apparatuses and methods can be related to implementing a binary neural network in memory. A binary neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the binary neural network and perform operations consistent with the binary neural network. The weights of the binary neural network can correspond to non-zero values.

Binary neural network in memory

A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.

Unused redundant enable disturb protection circuit

Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.

Indicating a blocked repair operation

An inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (CNN) to determine a classification from a plurality of classes for the captured image. Each of the plurality of classes indicates a type of a defect in the wafer. The system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. The system may also include a classification system to determine a classification from the plurality of classes for the training image. The encoder and decoder may be formed from a CNN autoencoder. The classification CNN and the CNN autoencoder may each be a deep neural network.

Apparatuses and methods for determining wafer defects

Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.

Selectable fuse sets, and related methods, devices, and systems

Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.

Error evaluation for a memory system

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Memory device with a memory repair mechanism and methods for operating the same

Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.

Memory apparatus with redundancy array

Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Adjustable column address scramble using fuses

Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.

Apparatus and techniques for programming anti-fuses to repair a memory device

Memory devices are disclosed. A memory device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, and electronic systems are also disclosed.

Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.

Memory devices are disclosed. A memory device may include a memory array including a number of memory cells partitioned into a number of memory segments. Each of the number of memory segments may include a redundant memory-cell group configurable to be accessed instead of a defective memory-cell group of the memory segment. The memory device may also include a set of latches configurable to indicate that a redundant memory-cell group of a memory segment of the number of memory segments is to be accessed instead of a defective memory-cell group of the memory segment. The set of latches may include segment latches configurable to indicate the memory segment or a status of the set of latches. The set of latches may also include address latches configurable to indicate the defective memory-cell group within the memory segment. Related systems and methods are also disclosed.

Memory devices with redundant memory cells for replacing defective memory cells, and related systems and methods

Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes a plurality of banks that each include (1) a plurality of memory cells and (2) a plurality of redundant cells configured to replace one or more target memory cells in the plurality of memory cells. A set of shared fuses and latches may be used to store a row address for each repair that may be implemented in one of the plurality of banks. A shared match circuit coupled to the set of shared latches and the plurality of memory banks may be configured to at least partially implement a row repair for the row address for a bank associated with a commanded operation.

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Boise, ID, United States of America

Seth A Eichmeyer