4ds Memory, Limited

4d-s, Ltd.

Seshubabu Desu

Michael Allen Van Buskirk

Lee Edward Cleveland

Dongmin Chen

Kurt Pfluger

Jean Yang-Scharlotta

An electronic device is disclosed. The electronic device includes a conductor, and a conductive oxide material electrically connected to the conductor. The conductive oxide materials is substantially amorphous, and the conductive oxide material includes first and second oxide materials. In addition, the first oxide material is different from the second oxide material. The electronic device also includes a second material, electrically connected to the conductive oxide material.

Conductive amorphous oxide contact layers

A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough.

Resistive memory device having an oxide barrier layer

An electronic storage memory device is disclosed. The memory device includes a first conductive layer, and also includes a memory layer connected to the first conductive layer, where the memory layer has a variable resistance, and where no amorphous layer exists between the first conductive layer and the memory layer.

Resistive memory device having a template layer

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions therethrough, where the first barrier layer is between the top electrode and the top contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, where the second barrier layer is between the memory layer and the bottom contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m.

Resistive memory device having a conductive barrier layer

A memory device is disclosed. The memory device includes a bottom contact. The memory device also includes a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure, where a first contact formed at an interface between the bottom contact and the memory layer is ohmic, and where a second contact formed at an interface between the memory layer and the top electrode is ohmic.

Resistive memory device having ohmic contacts

A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a lateral barrier layer connected to the bottom contact, the memory layer, and the conductive top electrode, where the lateral barrier layer is configured to substantially prevent conduction of ions or vacancies from the bottom contact, the memory layer, and the conductive top electrode to the lateral barrier layer.

Resistive memory device having side barriers

A memory device is disclosed. The memory device includes a bottom electrode. The memory device also includes a memory layer connected to the bottom electrode, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a retention layer between the memory layer and the top electrode, where the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction, and where the resistivity of the retention layer is less than 1&#xd7;10-4 ohm-m.

Resistive memory device having a retention layer

A resistive memory device is disclosed. The memory device comprises one or more metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation.

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Fremont, CA, United States of America

Seshubabu Desu