International Business Machines Corporation

Information Business Machines Corporation

Seshadri Subbanna

Richard Paul Volant

Kenneth Jay Stein

Kevin Shawn Petrarca

Robert Allen Groves

Gregory Gower Freeman

Manu J Tejwani

Kathryn Turner Schonenberg

Douglas Duane Coolbaugh

Jonathan Daniel Chapple-Sokol

Basanth Jagannathan

Timothy Joseph Dalton

Jeffrey Bowman Johnson

Richard Anthony Conti

Huajie Chen

Anil Kumar Chinthakindi

David R Greenberg

Peter Stevens Locke

Donna Rizzone Cote

David C Ahlgren

Stephen Bruce Brodsky

David Angell

Joseph Thomas Kocis

Keith M Walter

John C Bisson

Jeffrey P Gambino

Louis L Hsu

Ning Li

Fei Liu

Dominic Joseph Schepis

Jack Oon Chu

Subramanian Srikanteswara Iyer

John Michael Cotte

David Louis Harame

Qiqing Christine Ouyang

James Stuart Dunn

Wesley Charles Natzle

David Edward Kotecki

Steven G Barbee

Stephen Arthur St Onge

Louis DeWolf Lanzerotti

Peter B Gray

Hung-Yang Chang

Peter John Geiss

Kris V Srikrishnan

John M Aitken

Ryan Wayne Wuthrich

Paul Andrew Ronsheim

Shwu-Jen Jeng

Yajuan Wang

Fen Fen Jamin

John Chester Malinowski

Ronald W Knepper

James Anthony Tornello

Marc Waine Cantell

Waldemar Walter Kocon

Russell C Lange

Robert K Cook

Dale K Jadus

Bob H Yun

David M Rockwell

Zu-Jean Tien

Vijay P Kesan

Brian Cunningham

Jeffrey L Blouse

Subodh K Kulkarni

K T Schonenberg

A microfluidic system-on-a-chip includes signal processing, light generation and detection, and fluid handling functions formed on a single substrate. The disclosed integrated system has a smaller footprint than device structures where individual components are manufactured separately and then assembled. Moreover, the integrated system obviates alignment challenges associated with conventionally packaged architecture.

Integrated microfluidics system

A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.

Multi-level RF passive device

A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region. The anodized resistor thus formed has a sheet resistivity that is higher than that of the base resistor film.

Method for BEOL resistor tolerance improvement using anodic oxidation

A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.

Bipolar device having shallow junction raised extrinsic base and method for making the same

An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling

A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.

MEMS encapsulated structure and method of making same

A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.

Method of fabricating a polysilicon capacitor utilizing fet and bipolar base polysilicon layers

A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

Method of fabricating micro-electromechanical switches on CMOS compatible substrates

A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

BiCMOS integration scheme with raised extrinsic base

A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced width is achieved without the need of using advanced lithographic tools and/or advanced photomasks.

Nitride pedestal for raised extrinsic base HBT process

A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the &ldquo;chip side&rdquo; while the fixed bottom electrode is fabricated on a separated substrate &ldquo;carrier side&rdquo;. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and &ldquo;flipped over&rdquo;, aligned and joined to the &ldquo;carrier&rdquo; substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

Micro-electromechanical varactor with enhanced tuning range

Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers

Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.

Method of fabricating bipolar transistors with independent impurity profile on the same chip

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Brewster, NY, United States of America

Seshadri Subbanna