Applied Materials, Inc.

Advanced Micro Devices Corporation

Applied Material, Inc.

Seshadri Ramaswami

Jaim Nulman

Murali K Narasimhan

Vikram Pavate

Murali Abburi

Robin W Cheung

Glen T Mori

Kenny King-tai Ngan

Keith J Hansen

Philip Hsin-hua Li

Srinivas D Nemani

Michael Robert Rice

Klaus Florian Schuegraf

Darin A Chan

Claes H Bjorkman

Kenny King-Tai Ngan

Mohsen Salek

David F Kyser

Niranjan Kumar

Ajay Kumar

Zheng Xu

Ellie Y Yieh

Srinivas Gandikota

Mehul B Naik

Liang-Yuh Chen

Wei-Sheng Lei

Brad Eaton

Qiwei Liang

Todd J Egan

Arvind Sundarrajan

Saravjeet Singh

John Tolle

Sriskantharajah Thirunavukarasu

Shambhu Nath Roy

Viachslav Babayan

Chin Hock Toh

Rong Tao

Aparna Iyer

Tuck Foong Koh

Shay Assaf

Jen Sern Lew

Vanessa Pena

Amikam Sade

Andrew Cockburn

Gautam Pisharody

Thomas Kirschenheiter

Jingyu Qiao

Barry Hogan

Maureen Frances Breiling

Ying Yin Hui

Simon Hui

Ken Ngan

Philip Hsin-Hua Li

Daniel Philippe Cellier

Wei Hong

Andy Constant

Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Monolithic complementary field-effect transistors having carbon-doped release layers

A method includes forming, on a substrate by performing physical vapor deposition in vacuum, an absorber layer including copper (Cu), indium (In), gallium (Ga) and selenium (Se), forming a stack including the substrate and an oxygen-annealed absorber layer by performing in-situ oxygen annealing of the absorber layer to improve quantum efficiency of the image sensor by passivating selenium vacancies due to dangling bonds, and forming a cap layer over the oxygen-annealed absorber layer by performing physical vapor deposition in vacuum. The cap layer includes at least one of: GaO·Sn, ZnS, CdS, CdSe, ZnO, ZnSe, ZnInSe, CuGaS, InS, MgO, or ZnMgO.

Copper, indium, gallium, selenium (CIGS) films with improved quantum efficiency

Embodiments of the present disclosure relate to photovoltaic devices, CIGS containing films, and methods of manufacturing CIGS containing films and photovoltaic devices to improve quantum efficiency, reduce interface charges, electron losses, and electron re-combinations. The CIGS layers in the photovoltaic devices described herein may be deposited using physical vapor deposition, followed by in-situ oxygen annealing, and further followed by deposition of a cap layer over the CIGS layer without subjecting the CIGS layer to an air break.

Disclosed herein is an electrostatic chuck (ESC) carrier. The ESC carrier may comprise a carrier substrate having a first surface and a second surface opposite the first surface. A first through substrate opening and a second through substrate opening may pass through the carrier substrate from the first surface to the second surface. A first conductor is in the first through substrate opening, and a second conductor is in the second through substrate opening. The ESC carrier may further comprise a first electrode over the first surface of the carrier substrate and electrically coupled to the first conductor, and a second electrode over the first surface of the carrier substrate and electrically coupled to the second conductor. An oxide layer may be formed over the first electrode and the second electrode.

Method and apparatus for thin wafer carrier

Methods and apparatus form a photon absorber layer of a photodiode with characteristics conducive to applications such as, but not limited to, image sensors and the like. The absorber layer uses a copper-indium-gallium-selenium (CIGS) material with a gallium mole fraction of approximately 35% to approximately 70% to control the absorbed wavelengths while reducing dark current. Deposition temperatures of the absorber layer are controlled to less than approximately 400 degrees Celsius to produce sub-micron grain sizes. The absorber layer is doped with antimony at a temperature of less than approximately 400 degrees Celsius to increase the absorption.

Methods and apparatus for producing copper-indium-gallium-selenium (CIGS) film

Embodiments disclosed herein include photodiodes and methods of forming such photodiodes. In an embodiment, a method of creating a photodiode, comprises disposing an absorber layer over a first contact, wherein the absorber layer comprises a first conductivity type, and disposing a semiconductor layer over the absorber, wherein the semiconductor layer has a second conductivity type that is opposite from the first conductivity type. In an embodiment, the method further comprises disposing a hole blocking layer over the semiconductor layer, wherein the hole blocking layer is formed with a reactive sputtering process with a processing gas that comprises oxygen, and disposing a second contact over the hole blocking layer.

Method of creating CIGS photodiode for image sensor applications

A sealing structure is between a workpiece or substrate and a carrier for plasma processing. In one example, a substrate carrier has a top surface for holding a substrate, the top surface having a perimeter and a resilient sealing ridge on the perimeter of the top surface to contact the substrate when the substrate is being carried on the carrier.

Sealing structure for workpiece to substrate bonding in a processing chamber

An electrostatic chucking force tool is described that may be used on workpiece carriers for micromechanical and semiconductor processing. One example includes a workpiece fitting to hold a workpiece when gripped by an electrostatic chucking force by an electrostatic chuck, an arm coupled to the workpiece fitting to pull the workpiece through the workpiece fitting laterally across the chuck, and a force gauge coupled to the arm to measure an amount of force with which the workpiece fitting is pulled by the arm in order to move the workpiece.

Electrostatic chucking force measurement tool for process chamber carriers

Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.

Automated apparatus to temporarily attach substrates to carriers without adhesives for processing

A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

Method and system for wafer level singulation

Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.

Method of diced wafer transportation

Increased sidewall coverage by a sputtered material is achieved by generating an ionizing plasma in a relatively low pressure sputtering gas. By reducing the pressure of the sputtering gas, it is believed that the ionization rate of the deposition material passing through the plasma is correspondingly reduced which in turn is believed to increase the sidewall coverage by the underlayer. Although the ionization rate is decreased, sufficient bottom coverage of the by the material is maintained. In an alternative embodiment, increased sidewall coverage by the material may be achieved even in a high density plasma chamber by generating the high density plasma only during an initial portion of the material deposition. Once good bottom coverage has been achieved, the RF power to the coil generating the high density plasma may be turned off entirely and the remainder of the deposition conducted without the high density plasma. Consequently, it has been found that good sidewall coverage is achieved in the latter part of the deposition.

Method and apparatus for improving sidewall coverage during sputtering in a chamber having an inductively coupled plasma

A method and apparatus is provided for improving adherence of metal seed layers to barrier layers in electrochemical deposition techniques. The method includes depositing an adhesion layer continuously or semi-continuously without agglomeration onto a barrier layer prior to depositing a seed layer by controlling the substrate temperature, the chamber pressure, and/or the power delivered to a deposition chamber. Deposition of the adhesion layer prevents layer delamination which leads to agglomeration of the deposited layers and formation of voids in the high aspect ratio features.

Continuous, non-agglomerated adhesion of a seed layer to a barrier layer

A deposition system in a semiconductor fabrication system provides at least one electron gun which injects energetic electrons into a semiconductor fabrication chamber to initiate and sustain a relatively high density plasma at extremely low pressures. In addition to ionizing atoms of the extremely low pressure gas, such as an argon gas at 100 microTorr, for example, the energetic electrons are also believed to collide with target material atoms sputtered from a target positioned above a substrate, thereby ionizing the target material atoms and losing energy as a result of the collisions. Preferably, the electrons are injected substantially tangentially to the walls of a chamber shield surrounding the plasma in a magnetic field generally parallel to a central axis of the semiconductor fabrication chamber connecting the target to and the substrate. As the injected electrons lose energy ionizing the target material atoms, the electrons spiral inward toward a central region of the semiconductor fabrication chamber surrounding the central axis, forming an electron cloud in the central region. An arrangement of electromagnets may be positioned adjacent the walls of the chamber shield surrounding the plasma to generate the magnetic field. It is believed that the configuration of magnetic fields also keeps electrons from colliding with the walls of the chamber shield surrounding the plasma.

Sputtering method to generate ionized metal plasma using electron beams and magnetic field

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Saratoga, CA, United States of America

Seshadri Ramaswami