Samsung Electronics Co., Ltd.

Seryeun Yang

Sohyun Park

Hyeran Lee

Kyoungcho Na

A semiconductor memory device may include a substrate including an active pattern, the active pattern including first and second source/drain regions spaced apart from each other, a bit line that is electrically connected to the first source/drain region and crosses the active pattern, a storage node contact electrically connected to the second source/drain region, a spacer structure between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, an insulating pattern on the spacer structure and adjacent to the landing pad, and a liner between the insulating pattern and the landing pad. The insulating pattern may include an upper insulating portion and a lower insulating portion between the upper insulating portion and the spacer structure. The largest width of the lower insulating portion may be larger than the smallest width of the upper insulating portion.

Semiconductor memory devices

A semiconductor device includes: a stack including a conductive structure and an insulation structure stacked on each other on a substrate, wherein the stack extends in a first direction substantially parallel to an upper surface of the substrate; first, second and third spacers sequentially stacked on each other on a sidewall of the stack in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; and a capping pattern disposed on the second spacer, wherein: the second spacer is an air spacer including air, and an upper surface of a portion of the third spacer is substantially coplanar with an upper surface of the capping pattern.

Growing community of inventors

Hwaseong-si, South Korea

Seryeun Yang