Intel Corporation

Serkan Ozdemir

Qiong Cai

Nevin Hyuseinova

Ferad Zyulkyarov

Blas Cuesta

Marios Nicolaides

Ayose J Falcon

Dyer Rolan

A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and is served from the fast cache and not the slower next level memory. The requested memory extends the physical address space and is visible to and managed by the OS. The OS has the ability to make the requested memory visible to the user programs. The OS has the ability to manage the requested memory from the far memory cache as both a fully associative cache and a set associative cache.

Method for pinning data in large cache in multi-level memory system

Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request to initialize a system memory including a plurality of memory banks. Using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload is executed during the initialization of the system memory, the system characterization workload including a plurality of transactions directed towards the system memory. Embodiments of the invention may monitor target addresses of the plurality of transactions directed towards the system memory. One of the plurality of memory address mapping schemes is selected based, at least in part, on the target addresses of the plurality of transactions.

Workload adaptive address mapping

Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.

Memory imbalance prediction based cache management

Embodiments of the invention describe an apparatus, system and method for utilizing a utility and lifetime based cached replacement policy as described herein. For processors having one or more processor cores and a cache memory accessible via the processor core(s), embodiments of the invention describe a cache controller to determine, for a plurality of cache blocks in the cache memory, an estimated utility and lifetime of the contents of each cache block, the utility of a cache block to indicate a likelihood of use its contents, the lifetime of a cache block to indicate a duration of use of its contents. Upon receiving a cache access request resulting in a cache miss, said cache controller may select one of the cache blocks to be replaced based, at least in part, on one of the estimated utility or estimated lifetime of the cache block.

Utility and lifetime based cache replacement policy

Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.

Apparatus, system and method for adaptive cache replacement in a non-volatile main memory system

Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.

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Barcelona, Spain

Serkan Ozdemir