Xilinx, Inc.

Serhii Tumakha

Boon Yong Ang

Amit Ghia

Jan Lodewijk De Jong

Raymond C Pang

Hsung Jai Im

Sunhom Paak

A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process below the metal layer of the first node. The fuse structure can include a fuse link comprising a conductive material, positioned substantially perpendicular to each of the metal and conductive layers. An upper end of the fuse link couples to the first node and a lower end of the fuse link, that is distal to the upper end, couples to the second node.

Contact fuse one time programmable memory

A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein the diffusion material is electrically isolated from the substrate layer by at least one p-n junction. The fuse structure can include a cathode comprising conductive material overlaying the diffusion material. The fuse structure further can include a fuse link comprising conductive material overlaying the diffusion material, wherein a first end of the fuse link couples to the anode and a second end of the fuse link, that is distal to the first end, couples to the cathode.

Electrically programmable diffusion fuse

An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.

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San Jose, CA, United States of America

Serhii Tumakha