Advanced Micro Devices Corporation

Other

Mentor Graphics Corporation

Sergio R Ramirez

Walter Stuart Schopfer

Yan Zhou

Michael A Nix

Merle L Miller

Emanuel E Shah

V Vijayakumaran Nair

Imran Baoai

Provided are apparatuses and methods for digital FM modulation. In one example, a message signal is integrated by an integrator to transform the message signal into a complex signal. The complex signal may include at least two complex components that may interfere to produce an FM modulated carrier signal. Hence, in this example, the method and apparatus for digital FM modulation may produce an FM modulated carrier signal without phase shifting. In another example, a lookup table is not necessary for modulation of the carrier signal.

Digital FM modulator

A protection device for vertically standing lamps devices is described. The protection device consists of a switch or other means of interrupting the electrical current in case of a fall. The preferred embodiment of the invention is a normally open switch installed at the base of the lamp. This switch is closed by the action of lamp's own weight.

Safety mechanism for lamps

An apparatus for setting a device into a test mode. The apparatus has a first input port for receiving a fixed, constant signal during a normal mode of the device, and for receiving a non-fixed, clocked signal so as to set the device into a test mode. The apparatus also has a second input port for receiving a non-fixed, clocked signal during the normal mode and for receiving a fixed, constant signal so as to set the device into the test mode. When both the first input port receives the non-fixed, clocked signal and the second input port receives the fixed, constant signal for a predetermined amount of time, the device is placed into the test mode.

Circuit for setting a device into a test mode by changing a first port

A positive edge triggered flip flop which includes a master stage and a slave stage. The master stage includes an inverter that receives a clock input (C), and a first NAND gate having one input port for receiving a data input (D). The master stage also includes a second NAND gate and a first NOR gate that have their respective output connected to an input port of the other gate. The slave stage receives an inverted clock output from the inverter of the master stage. The slave stage includes a third NAND gate and a second NOR gate that also have their respective output connected to an input port of the other gate. An output value (Y) is read from the output of the second NOR gate.

Positive edge triggered flip flop

An inertial delay circuit includes a negative glitch removing circuit connected in series with a positive glitch removing circuit. The negative and positive glitch removing circuits are respectively configured to pass only negative and positive pulses of an input signal having a pulse width greater than a pre-determined width. The negative glitch removing circuit passes its input through a delay line and performs a logical OR on its input and the delayed signal. The positive glitch removing circuit passes its input through a delay line and performs a logical AND on its input and the delayed signal. The glitch removing circuits may further include respective pulse width restoring circuits to restore the pulses passing therethrough to their original widths.

Inertial delay circuit for eliminating glitches on a signal line

A fuse protection and fuse blowing circuit includes a fuse register which has an additional fuse with respect to other fuse registers used in the system. The additional fuse has an output which indicates a blown/not blown state of the additional fuse, and that output is fed back to a blow enable input of each of the other fuses in the fuse register and the other fuse registers. When the additional fuse is set to the blown state, none of the other fuses are allowed to be blown, thereby protecting the device against any accidental blowing of fuses.

Apparatus for preventing accidental or intentional fuse blowing

A power-cross detection circuit includes a zero crossing detection circuit for detecting a first zero crossing of the current from a first positive half-cycle to a first negative half-cycle, a second zero crossing of the current from a second positive half-cycle to a second negative half-cycle, and a third zero crossing of the current from a third positive half-cycle to a third negative half-cycle and a circuit for detecting a voltage level and outputting a first signal when the voltage level exceeds a predetermined voltage level, between the first zero crossing and the second zero crossing and between the second zero crossing and the third zero crossing. The zero crossing detection circuit outputs a second signal based on the first, second and third zero crossings. The power-cross detection circuit also includes a logic circuit for outputting a third signal when the time interval between the first zero crossing and the second zero crossing and between the second zero crossing and the third zero crossing is between 14 milliseconds and 24 milliseconds. A power-cross condition is detected based on the first, second and third signals.

Protection circuit for telephone systems

An apparatus for determining a power cross condition during a ringing state of a telephone. The apparatus also is capable of distinguishing a true power cross condition from a short loop ringing condition, by including a first path for receiving a signal indicative of a voltage across a ring feed resistor exceeding a predetermined value, and determining if that voltage is in an active state for a predetermined amount of time (i.e., 14 milliseconds). The apparatus also includes a second path for receiving a first and second current that flow respectively across a first and second sense resistor connected to opposite ends of the ring feed resistor. On the second path, the first and second currents are subtracted, converted to a digital value, filtered, and compared to a threshold value to determine if a ring trip has occurred. If so, the potential ring trip is sent to a persistence timer circuit, for checking if it is in an active state for a predetermined amount of time (i.e., 104 milliseconds). If either of the first and second paths indicate a ring trip, then the apparatus outputs a ring trip detection signal. The apparatus also is configured to work with a power cross validation circuit, which may be connected on a third path for switching ring relays quickly to save components on the telephone lines during a power cross occurrence.

Integrated ring detection circuit and power cross detection circuit with

A multiplexed delta-sigma modulator for performing analog to digital conversion on a plurality of input analog signals. These input analog signals are input to a multiplexer, where the input analog signals are converted into a single, time-division multiplexed analog signal. The time-division multiplexed analog signal is then received by the delta-sigma modulator, which oversamples the input signal and outputs a time-division multiplexed digital signal. The time-division multiplexed digital signal is then sent to a decimator which outputs a time-division multiplexed digital signal at a rate corresponding to the Nyquist rate of the input analog signals. The signal is sent from the decimator to a first down-sampler, and then to a demultiplexer, where the time-division multiplexed, decimated signal is sent to the appropriate output port of the demultiplexer at a sequential rate corresponding to the sequential rate utilized by the input multiplexer. At each output port of the demultiplexer there is a second down-sampler operating at a predetermined rate to recover each of the plurality of digital output signals corresponding to the plurality of input analog signals.

Multiplexed delta-sigma modulator

A regenerative comparator provides the capability of operating faster than a traditional regenerative comparator and the hysteresis points can be individually set and fine tuned. The regenerative comparator includes a current mirror having an input transistor connected to first and second output transistors, a first and second reference current sources which are set at a first and second predetermined level, respectively. An outputs of the first and second output transistors are provided to the latch through an inverter. The output of the latch transitions from a first logical output state to a second logical output state when an input current increases from a magnitude less than the first predetermined level to a magnitude greater than the first predetermined level.

Digital regenerative comparator

A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The latch circuit is formed of a first clocked half-latch, a second clocked half-latch and an inverter for storing a binary output signal. The first clocked half-latch is responsive to a first clock phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch is responsive to a second clock phase signal for transferring a binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The control circuit requires only one transistor and two input signals to perform its required functions. When the input complement signal is High and the first phase input clock signal is High, an enable signal is sent to the first clocked half-latch, thereby enabling the count process. Any number of these counter cells can be arranged to form an N-bit counter circuit.

Counter cell and counter circuit

An apparatus for controlling the magnitude of a metering signal used in a communication system includes a high pass filter and a threshold detector. The apparatus is preferably integrated on to a subscriber line audio-processing circuit (SLAC device) which is used on a line card. The device is operable with either 12 kHz of 16 kHz metering signals. The high pass filter preferably includes a shift register and an adder. The level detector preferably includes a shift register, an OR gate and an AND gate. The device preferably is utilized to reduce the echo or reflection caused by the variable impedance of subscriber lines in telephone communication systems.

Growing community of inventors

Austin, TX, United States of America

Sergio R Ramirez