Sgs-thomson Microelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Stmicroelectronics S.r.l.

Co. Ri. M. Me.

Chrysler Corporation

Sgs-thomson Microelectronics Limited

Sgs-thomson Microelectronics S.p.a.

Co.ri.m.me. Consorzio Per La Ricerca Sulla Microelettronica Nel

Consorzio Per La Ricerca Sulla Microelettronica

Sergio Palara

Stefano Sueri

Natale Aiello

Mario Paparo

Raffaele Zambrano

Salvatore Scaccianoce

Vito Graziano

Salvatore Raciti

Michele Zisa

Donato Tagliavia

Roberto Pellicano

Davide Giuseppe Patti

Giuseppe Ferla

Salvatore Leonardi

Salvatore Rosario Musumeci

Atanasio La Barbera

Giuseppe Scilla

Angelo Pinto

Roberto Pellicano'

Paolo Monaco

Benedetto P DiCicco

Pietro Lizzio

A method for manufacturing a thick oxide layer on a semiconductive substrate is presented. The method comprises the formation of at least one layer of dielectric material on said substrate, followed by formation of a plurality of trench regions of a predetermined width in the substrate. A plurality of corresponding walls of semiconductive material of a second predetermined width are delimited. Finally, the semiconductor is submitted to a thermal treatment to oxidize said walls.

Manufacturing method for a thick oxide layer

The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

Method and apparatus for the selective doping of semiconductor material by ion implantation

A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate and an N type epitaxial layer forming a surface. The transistor has a P type buried collector region astride the substrate and the epitaxial layer; a collector sinker insulating an epitaxial tub from the rest of the wafer; a gain-modulating N type buried base region astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N.sup.+ type base sinker extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region, forming a constant or variable dope concentration profile of the buried base region, providing or not a base sinker, and varying the form and distance of the base sinker from the emitter region.

Vertical PNP transistor and relative fabrication method

A monolithically integrated power device for driving electrical loads includes a power stage having a high-voltage bipolar transistor and a low-voltage auxiliary transistor cascade-connected and inserted between a first power supply terminal and a second power supply terminal of the device. The power device also includes a driver circuit for the power stage having an input connected to an input terminal of the device. In accordance with the present invention the device includes a circuit for protection thereof against an excessive temperature rise and controlling power down of the power stage. It includes specifically a temperature sensing circuit which generates a signal dependent on the temperature present in the device, a comparator circuit which receives this signal and compares it with a reference voltage and at least a first switch circuit generating an interdiction signal when the temperature in the device exceeds a preset maximum value and which is interlocked with an output of the comparator circuit and connected functionally through its output to the power stage. The device is advantageously usable in a fluorescent lamp driving circuit, that is to say in the so-called 'lamp ballast'.

Bipolar power device having an integrated thermal protection for driving

A power integrated circuit including a substrate of semiconductor material having a first conductivity type on which is formed a first epitaxial layer of the same conductivity type. In a first portion of the first epitaxial layer are formed first and second diffused regions having respectively first and second conductivity type. The first and the second diffused regions are isolated from a power stage included partially in a second portion of the first epitaxial layer by an annular region having the second conductivity type. Over the first epitaxial layer is formed a second epitaxial layer having the first conductivity type in which are extended the first and the second diffused regions to permit forming a control circuitry for the power stage.

Power integrated circuit

A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region a surface region, and a first vertical diffusion region connecting the buried layer to the surface region. A second vertical diffusion region connects the buried emitter layer periphery to a first surface contact, while the surface emitter region is contacted, along three peripheral sides thereof, by a second surface contact. The transistor current flows from the substrate, through the base to the buried emitter region. It is then conveyed into the vertical region, which represents a resistive path, and on reaching the surface region splits between two resistive paths included between the vertical region and the surface contacts. These resistive paths form in combination the current sensing resistor incorporated to the transistor, whose terminals are led to the first and second surface contacts, respectively.

Vertical bipolar power transistor with an integrated sensing circuit

A driver circuit delays the turning on of a MOS transistor by utilizing the time-wise pattern of the circuit input signal rather than generating a delay within the circuit itself. A threshold type of circuit element is arranged so that no current flows toward or from, depending on the type of the MOS transistor, the control terminal before the voltage at the circuit input exceeds a predetermined value. This is achieved, for example, by coupling a Zener diode serially to the control terminal. Where the input signal is of a kind which increases with a degree of uniformity, the time required to exceed that threshold will correspond to the desired delay. Thus, the driver circuit can match the dynamic range of the input signal automatically.

Driving circuit and method for driving a MOS transistor with delayed

An overvoltage limiting circuit having first and second terminals to produce a temperature-stable voltage proportional to an overvoltage condition. The overvoltage limiting circuit includes a first transistor having a first terminal connected to the first terminal of the circuit, a second terminal kept at a reference voltage relative to the second terminal of the circuit, and a control terminal coupled with the second terminal of the circuit through equivalent resistor means whose value depends on the value of the temperature-stable voltage so that the first transistor has a temperature-stable breakdown voltage.

Circuit for limiting an overvoltage on a control switch connected in

A method for detecting the presence of a spark in an electronic ignition system. The method consists of generating an overvoltage event and then generating a voltage signal proportional to the overvoltage event. The onset of the overvoltage event is detected by comparing the voltage signal to a starting threshold voltage and in response is provided a first signal at a high logic level. The first signal is maintained at said high logic level during the time duration of the overvoltage event. The termination of the overvoltage event is detected by comparing the voltage signal to an ending threshold voltage, which is lower than the starting threshold voltage and proportional to a supply voltage of the electronic ignition system, and in response is provided a second signal at a low logic level. The time duration of the first signal is detected and then the presence of a spark is signalled if said time duration exceeds a reference value.

Method for detecting the presence of a spark in an electronic ignition

A circuit for use with an ignition system to enable detection of an overvoltage condition in the primary winding of an ignition coil caused by opening of a power switch connected to the primary winding. The circuit senses the overvoltage condition by comparing the voltage on the primary winding to a first threshold voltage and produces a signal at an output terminal indicative of the presence of the overvoltage condition. The output terminal is maintained at a high logic level upon detection of an overvoltage condition and throughout the time duration of the overvoltage condition, and drops to a low logic level when the voltage on the primary winding falls to a second threshold voltage, which is lower than the first threshold voltage. Comparison circuitry is provided for sensing the overvoltage condition by reference to fixed voltage values. Logic circuitry responds to the comparison circuitry to produce the appropriate logic levels at the output terminal.

Circuit for detecting an overvoltage on a switched inductive load

A start up circuit causes a MOS transistor to be turned on by sensing local electrical quantities thereof, specifically the potential at the drain terminal of the MOS transistor. A small current is injected into the control terminal of the MOS transistor when the potential at the drain terminal is high. For the purpose, an electric network is arranged to couple these two terminals together.

Starting circuit and method for starting a MOS transistor

A device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor and an N-channel MOSFET transistor in an emitter switching configuration, both being vertical conduction types. The bipolar transistor has its base and emitter regions buried; the MOSFET transistor is formed with an N region bounded by the base and the emitter regions and isolated by a deep base contact and isolation region. To improve the device performance, especially at large currents, an N+ region is provided which extends from the front of the chip inwards of the isolated region and around the MOSFET transistor. In one embodiment of the invention, a MOSFET drive transistor is integrated which has its drain terminal in common with the collector of the bipolar transistor, its source terminal connected to the base of the bipolar transistor, and its gate electrode connected to the gate electrode of the MOSFET transistor in the emitter switching configuration.

Integrated device with a bipolar transistor and a MOSFET transistor in

An integrated circuit including a power stage, a low-voltage component separated from the power stage by an isolating region and a reference potential region at a reference potential. The power stage includes an N-type substrate region which may be biased to a terminal voltage with respect to the reference potential and the isolating region has P-type conductivity. The low-voltage component includes an N-type input region receiving an input voltage. The input voltage and the terminal voltage may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors. To prevent turning on of the parasitic transistors, switchable conductive paths are interposed between the isolating region on the one hand, and the substrate region, the input region and the reference potential region on the other, for electrically connecting the isolating region to one of the substrate region, input region and reference potential region which presents instant by instant the lowest potential.

Circuit for preventing operation of parasitic components in integrated

A circuit to limit the maximum current passed from a power transistor (T'p) to a load (ZL) which is connected to an output terminal of the transistor. The circuit includes an error amplifier (1'), a driver circuit (P') for the transistor (T'p), and a current detector for detecting the current (IL) flowing through the load (ZL). The current detector is provided with at least first and second terminals, includes a circuit block (2) having an input terminal connected to the control terminal of (T'p) and an output terminal connected to the current generator internal to the amplifier (1'), one input (B') of the amplifier (1') being connected to the first terminal of (Rs) and the other input (A') connected to the second terminal of (Rs). The introduction of the circuit block lowers the open-loop system gain making it stable and producing a smooth reduction of any rise in the load current (IL).

Power transistor current limiter

A circuit is provided for protecting against an increase in collector current for an integrated circuit containing a power switching device. The power device drives an inductive load connected to a power supply, and is connected to a control circuit for switching the power device on and off. The protection circuit contains a clamping circuit for deactivating the control circuit and switching the power device off when the current flowing through the power device reaches a preset maximum value. In addition, a circuit is provided for inhibiting the operation of the clamping circuit for a preset time interval after the power device has been switched on, and for keeping the clamping circuit in operation during voltage undershoots caused by the inductive load following the switching of the powered device off.

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Acicastello, Italy

Sergio Palara