Cisco Technology, Inc.

Sergio D Camerlo

Wheling Cheng

Roger Antoine Karam

Yida Zou

Luca Cafiero

Hsing-Sheng Liang

Gary L Myers

Bangalore J Shanker

Lekhanh Dang

Bobby Parizi

David K Sanders

Irfan Elahi

A method of fabricating a printed circuit board having a coaxial via is disclosed. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.

Method for fabricating a printed circuit board having a coaxial via

In a System-in-Package (SiP) module, a method and a system for optimizing the timing margin of source-synchronous interface clocks is provided. Clock signals generated by first device are transmitted to serpentine traces located on a Printed Circuit Board (PCB) which adjusts the active edge of one signal relative to another signal. The serpentine trace introduces a delay in the clock signal thereby optimizing timing margins. By providing access to signals otherwise internal the SiP, testing and signal verification is also simplified.

Method and system to optimize timing margin in a system in package module

A method of fabricating a printed circuit board having a coaxial via, includes. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.

An electronic interconnection system for delivering high-current power and ground voltages using a non-bottom side of a chip package substrate. The system includes a printed wiring board (PWB), a chip package, and a bridge lead. The PWB has at least a first and a second contact pad. The chip package includes a chip and a package substrate. The chip is mounted onto the package substrate and the package substrate has a bottom surface having at least a first contact pad and a second surface having at least a second contact pad. The first contact pad of the PWB and the first contact pad of the package substrate are coupled together. The bridge lead couples the second contact pad of the PWB with the second contact pad of the package substrate. The bridge lead may be selected from styles including flying lead, edge wiping, top wiping, and double wiping.

Method and apparatus for delivering high-current power and ground voltages using top side of chip package substrate

A backplane assembly includes a main backplane having a first power conductor, a backplane strip having a second power conductor, and connecting members disposed between the main backplane and the backplane strip. The connecting members hold the backplane strip in a fixed position relative to the main backplane and electrically connect the first power conductor and the second power conductor. In one arrangement, the connecting members include source standoffs which extend from a source area of the main backplane to the backplane strip, and target standoffs which extend from a target area of the main backplane to the backplane strip. The source and target standoffs and the second power conductor provide a current path which increases current carrying capacity from the source area to the target area above that provided by the first power conductor alone. Thus, the backplane assembly is well-provisioned for distributing high currents to circuit boards.

Techniques for distributing current in a backplane assembly and methods for making the same

A circuit board assembly includes a printed circuit board (PCB). The PCB has a pad layout which includes a set of pads arranged in a two-dimensional array having at least two pads in a first direction and at least two pads in a second direction that is substantially perpendicular to the first direction. Each pad has (i) a central portion and (ii) multiple lobe portions integrated with the central portion and extending from the central portion of that pad. The circuit board assembly further includes a circuit board component mounted to the pad layout via a set of solder joints. The above-described pad layout (or land pattern) is well-suited for soldering to a variety of AAP devices (e.g., either a CCGA device or a BGA device).

Techniques for mounting an area array package to a circuit board using an improved pad layout

A circuit board is configured to exchange data signals with a circuit board component through data signal contacts located between the circuit board and a primary surface of the circuit board component. The circuit board has power supply signal contacts that are configured to carry power supply signals to the circuit board component through a secondary surface of the circuit board component. A signal carrier connects the power supply signal contacts of the circuit board with the circuit board component through the secondary surface of the circuit board component. Such a configuration allows the circuit board component to receive a relatively large amount of power while maintaining the number of data signal contacts dedicated for transmission of data signals between the circuit board and circuit board component.

Methods and apparatus for providing a signal to a circuit board component

A circuit board assembly has a circuit board coupled to a support plane and defining a space between the circuit board and the support member. A circuit board component mounts to the circuit board and is oriented within the space defined by the circuit board and the support plane. A heat pipe assembly, located within the defined space, has a relatively high thermal conductivity, compared to other thermally conductive materials, and transfers heat from the circuit board component to the support plane or carrier tray associated with the circuit board. The heat pipe assembly has an input portion that contacts the circuit board component and an output portion that contacts the support plane. The heat pipe assembly also has a compliant portion having a lower stiffness relative to the stiffness of either the input portion or the output portion. The compliant portion of the heat pipe assembly allows for displacement of the input portion relative to the output portion to limit the amount of stress generated by the heat pipe assembly on the circuit board component.

Methods and apparatus for cooling a circuit board component using a heat pipe assembly

A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Method and apparatus for clock uncertainty minimization

Method and apparatus for clock uncertainty minimization with a clean

A precision voltage regulator comprises a three terminal regulator coupled to a voltage divider. The voltage divider has two composite resistors, each of which comprises a plurality of matched value resistors fabricated on a common substrate, mixed in series and parallel configurations. The resultant voltage divider produces a wide range of divider ratios, while preserving a divider ratio which is independent of temperature and tolerance effects.

Voltage setpoint error reduction

A system for the distribution of VTT termination voltage for a GTL bus system includes a plurality of GTL signal lines, a plurality of first termination resistors, and a plurality of second termination resistors. The GTL signal lines have a first end and a second end. The resistors have a signal end and a VTT end. The first end of the signal line is connected to the signal end of the first resistor. The second end of the signal line is connected to the signal end of the first resistor. A plurality of nodes are formed from the VTT ends of the first and second resistors. These nodes may be formed in many different ways, and in many different numbers. The nodes are each driven with a separate VTT supply, and the nodes are interconnected such that a failure in the power supply furnishing power to one node does not affect the other nodes, and does not affect the operation of the system consuming this VTT voltage.

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Cupertino, CA, United States of America

Sergio D Camerlo