Intel Corporation

Sergio Carlo Rodriguez

Fabrice Paillet

Gerhard Schrom

Alexander Lyakhov

James Keith Hodgson

Anand Ramasundar

Po-Cheng Chen

Anant S Deval

Manohar Ruben Castelino

Cary Renzema

Sarath S Makala

Sidhanto Roy

Keith Hodgson

Ravi L Sahita

Vedvyas Shanbhogue

Harish Krishnamurthy

Chee Lim Nge

Michael Zelikson

Amit Kumar Jain

Harshawardhan Vipat

Vikas Gupta

George Matthew

Sami Hyvonen

Nimrod Angel

Rachid Rayess

Christopher J Mandic

Pushkar Dixit

Jason Muhlestein

Alex Santiago Rodriguez

Saravanan Ramamoorthy

Ruthvin Jeevan Suvarna

Embodiments herein relate to a feedback loop in a digital voltage regulator for controlling an output voltage. To avoid instability at light current loads, a gain of the loop is reduced as a power gate code indicates a reduced number of branches in set of current sources are enabled. In an example implementation, the code is classified into one range of a number of ranges, and the gain is set based on the one range. The gain can decrease each time the code enters a lower range, as indicated by the code crossing a threshold or predetermined value. For example, the gain can decrease by half each time the code enters a lower range.

Adaptive gain for compensation in a digital voltage regulator

A reduced-size replica of power gate transistors may be used within a closed-loop voltage regulator to measure the average current delivered by the transistors in the non-replica power gate. The measured current is compared against a known reference current, and a feedback loop is used to modify the gate bias of the power gate and replica power gate transistors. An improved current sensing power gate replica solution may include measuring current from a small replica of the power gate and extrapolating the total current by digitally multiplying the replica current by the ratio of the size of the enabled power gates to the size of the replicas. The current through the replicas, which substantially matches the current in equivalent power gate devices, may be collected on an analog bus and conducted across a known resistor to generate a voltage that determines an estimated current of the power gate devices.

Digital voltage regulator current sensing and regulation

An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.

DVR with pulsed control and gradual NLC

A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

Differential to single-ended high bandwidth compensator

Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Apparatus and method for proactive power management to avoid unintentional processor shutdown

An apparatus is provided which comprises: at least two switches in series between an input voltage node and a ground terminal; an inductor coupled between a mid-point of the at least two switches and an output terminal; a first circuitry to compare a current through the inductor with a threshold current, and to control one or both of the at least two switches, based at least in part on the comparison; and a second circuitry to randomly vary the threshold current over consecutive cycles of switching of the at least two switches.

Reducing electromagnetic interference in switching regulators

Technologies for monitoring system API calls include a computing device with hardware virtualization support. The computing device establishes a default memory view and a security memory view to define physical memory maps and permissions. The computing device executes an application in the default memory view and executes a default inline hook in response to a call to an API function. The default inline hook switches to the security memory view using hardware support without causing a virtual machine exit. The security inline hook calls a security callback function to validate the API function call in the security memory view. Hook-skipping attacks may be prevented by padding the default inline hook with no-operation instructions, by designating memory pages of the API function as non-executable in the default memory view, or by designating memory pages of the application as non-executable in the security memory view. Other embodiments are described and claimed.

Technologies for preventing hook-skipping attacks using processor virtualization features

Systems, methods, and computer program products that provide for the use of a type 2 VMM to de-link or isolate underlying processor hardware from an operating system. This may allow the launching of a task that requires direct access to processor hardware, where such access requires the absence of an operating system. Such a task may take the form of a type 1 VMM, such as an information security or integrity VMM, e.g., an anti-malware VMM.

Systems, methods and computer program products for bootstrapping a type 1 virtual machine monitor after operating system launch

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Hillsboro, OR, United States of America

Sergio Carlo Rodriguez