Altera Corporation

Other

Intel Corporation

Sergey Yuryevich Shumarayev

Wilson Wong

Tim Tri Hoang

Rakesh H Patel

Thungoc M Tran

Weiqi Ding

Simardeep Maangat

Tony K Ngai

Wei-Jen Huang

Tin H Lai

Allen K Chan

Bruce B Pedersen

Chong H Lee

James G Schleicher

Victor Maruri

Peng T Li

Thomas Henry White

Kazi Asaduzzaman

Tien Duc Pham

David Wolk Mendel

Mei Luo

Mingde Pan

Richard G Cliff

Ramanand Venkata

Jim Park

Sriram Narayan

Toan Thanh Nguyen

Masashi Shimanouchi

Arch Zaliznyak

Michael David Hutton

Leon Zheng

Andrew Leaver

Peter J Kazarian

James Park

Shoujun Wang

William W Bereza

Xiaoyan Su

Jon M Long

Vinson Chan

Bill W Bereza

Yanjing Ke

Ali Atesoglu

Neville Carvalho

Mengchi Liu

Joel Martinez

Doris Po Ching Chan

In Whan Kim

Wanli Chang

Kumara Tharmalingam

Shou-Po Shih

Sammy S Cheung

Paul B Ekas

Mike Peng Li

Zhi Y Wong

Sharat Babu Ippili

Kyung Suk Oh

Hae-Chang Lee

Stephen D Brown

Boon Jin Ang

Tad Kwasniewski

Ning Xue

Henry Y Lui

Curt Wortman

Yu Xu

Michael Menghui Zheng

Andy Turudic

Wei Li

Surinder Singh

Edwin Yew Fatt Kok

Allan Thomas Davidson

Teng Chow Ooi

Mian Z Smith

Eng Huat Lee

Guang Chen

Chuan Khye Chai

Lip Kai Soh

Bruce B Pederson

Sangeeta Raman

Lawrence David Smith

Daniel Tun Lai Chow

Vinh Van Ho

Yuming Tao

Kang-Wei Lai

Kalyan Kankipati

Kenneth T Daxer

Tee Wee Tan

Yew Fatt (Edwin) Kok

Seungmyon Park

Kwong-Wen Wei

Siriram Narayan

Chee Hong Aw

John Dung-Ngoc Lam

Miao Li

Mengchi Lui

The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

Universal transceiver container

The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit isconfigured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Apparatus and methods for calibrating analog circuitry in an integrated circuit

Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel. In some embodiments, the FPOA may improve flexibility by performing such functions without reconfiguring the data utilization circuit.

Integrated circuit device with field programmable optical array

The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

High-speed serial data signal receiver circuitry

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g.,parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.

Phase-locked loop architecture and clock distribution system

A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Transceiver system with reduced latency uncertainty

One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Flexible receiver architecture

An analog test network includes a conductor. The conductor is coupled to provide a first analog signal from a circuit under test to an analog-to-digital converter circuit. The analog-to-digital converter circuit is operable to generate a first digital signal based on the first analog signal. A control circuit is operable to generate a second digital signal based on the first digital signal. A digital-to-analog converter circuit is operable to generate a second analog signal based on the second digital signal. The conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the circuit under test.

Analog signal test circuits and methods

A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Simulation tool for high-speed communications links

One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.

On-die jitter generator

A system and a method of manufacture of an integrated circuit system includes: a supply grid connected to an active component of an integrated circuit die; a high voltage capacitor connected to the supply grid; a low voltage decoupling capacitor connected to the supply grid; a pass gate gating the low voltage decoupling capacitor; and a pass gate control for controlling the pass gate to cause the high voltage capacitor and the low voltage decoupling capacitor to stabilize voltage of the supply grid during activity of the active component.

Integrated circuit system with dynamic decoupling and method of manufacture thereof

Growing community of inventors

Los Altos Hills, CA, United States of America

Sergey Yuryevich Shumarayev