Freescale Semiconductor,inc.

Nxp Usa, Inc.

Intel Corporation

Freesacle Semiconductor, Inc.

Sergey Sofer

Songnan Yang

Michael Priel

Dan Kuzmin

Valery Neiman

Asher Berkovitz

Yehim-Haim Fefer

Yefim-Haim Fefer

Dov Tzytkin

Eyal Melamed-Kohen

Anton Rozen

Leonid Fleshel

Noam Sivan

Yefim Fefer

Yair Rosenbaum

Emil Yehushua

Shahar Wolf

Vlad Goldman

Alex Nayshtut

Oleg Pogorelik

Avishay Sharaga

Shahar Porat

Avi Priev

Yoav Weizman

Leonid Smolyansky

Miguel Ballesteros

Yoav Miller

Gennady Goltman

Michael Zimin

Mikhail Bourgart

Avi Elazary

Ami Dabush

Moshe Lavi

Shai Sade

Moty Groissman

Boris Zapesochini

Pavel Livshits

Dov Tyztkin

There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state. There is also provided an associated method of performing at-speed scan testing of an integrated circuit.

Method and apparatus for at-speed scan shift frequency test optimization

Described herein are architectures, platforms and methods for offloading process or application from a near field communication (NFC) master device for proxy delegation to a proxy NFC device.

Near field communications (NFC)-based offload of NFC operation

A method and apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, IC, design. The method comprises calculating at least one weighted rise activity, WRA, value for at least one region of the IC design based at least partly on rising gate transitions within the at least one region of the IC design when the test pattern is applied thereto, calculating at least one weighted fall activity, WFA, value for the at least one region of the IC design based at least partly on fall gate transitions within the at least one region of the IC design when the test pattern is applied thereto, and validating the test pattern based at least partly on the WRA value and the WFA value.

Method and apparatus for validating a test pattern

Some demonstrative embodiments include apparatuses, systems and/or methods of detecting an activity of a wireless communication device. For example, a Near Field Communication (NFC) device may include a transmitter to transmit information to a polling device by modulating a carrier signal emitted by the polling device; a sensor to sense a plurality of sensed modulation levels of the carrier signal; and a controller to detect an activity of an other NFC device based on the sensed modulation levels.

Apparatus, system and method of detecting an activity of a wireless communication device

A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative/Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element.

Method and apparatus for calculating delay timing values for an integrated circuit design

An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load. A method of operating the electronic device is also described.

Electronic device and method for operating a power switch

A method generates scan patterns for testing an electronic device called DUT having a scan path. A scan tester is arranged for executing a scan shift mode and a capture mode. A scan test interface has a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern. The method determines at least one power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode, and generates, in addition to the scan pattern, a scan clock pattern indicative of stretching the power shift cycle. Advantageously, a relatively high scan shift frequency may be used while avoiding detrimental effects of said voltage drop by extending the respective power shift cycle, whereby test time and yield loss are reduced.

Scan test system with a test interface having a clock control unit for stretching a power shift cycle

An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

Integrated circuit comprising an IO buffer driver and method therefor

The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the associated first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.

Processor core arrangement, computing system and methods for designing and operating a processor core arrangement

The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.

Clock source, method for distributing a clock signal and integrated circuit

The invention provides a method for launch-off-shift at-speed scan testing for at least two scan chains of an integrated circuit comprises iteratively shifting set values for functional elements of a first one of the scan chains clocked with a shift clock, iteratively shifting set values for functional elements of a second one of the scan chains clocked with the shift clock, launching an at-speed scan test clocked with a functional clock for the first one of the scan chains at a last shift cycle of the first one of the scan chains, delaying the last shift cycle for the second one of the scan chains for a predetermined time span, launching an at-speed scan test clocked with a functional clock for the second one of the scan chains at the last shift cycle of the second one of the scan chains, capturing the sample values of the functional elements of the first and second scan chains after the last shift cycle of the scan chains.

Method and control device for launch-off-shift at-speed scan testing

Processing logic circuit has State Retention Power Gating logic circuit including at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state. The processing logic circuit includes a memory operable to store collected state information about the at least a portion of the processing logic circuit, and logic circuit operable to rearrange the collected state information data for scan chains shorter than a longest scan chain, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.

Method and apparatus for scan chain data management

A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

An electronic device comprises one or more functional units, each functional unit being clocked by a respective clock signal. The electronic device further comprises a monitoring unit for providing a real-time estimate of an electrical current consumed by the functional units. The monitoring unit provides the real-time estimate on the basis of characteristic signals. The characteristic signals may comprise one or more of said clock signals, or one or more clock generating signals used to generate said clock signals. The electronic device may further comprise a power regulator responsive to the real-time estimate. A method of estimating in real-time an electrical current consumed by one or more functional units is also described.

Electronic device and method

The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.

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Rishon Lezion, Israel

Sergey Sofer