Lda Technologies Ltd.

Xcelor LLC

Arista Networks, Inc.

Metamako General Pty Ltd Acn 163 573 331 in Its Capacity As General Partner of Metamako Technology LP Abn 11 872 058 101

Sergey Sardaryan

Vahan Sardaryan

Mariya Sukiasyan

Robert James Walker

Stefan Josef Gratzl

Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

Systems and methods for timing a signal

A digital crosspoint switch of a network switching system (NSS) replicates input data received via a first network interface to a first data processing port of a data processing card. The input data includes a digital market data feed comprising market-data packets. The crosspoint switch has internal crosspoint ports and external crosspoint ports. The data processing card includes a programmable logic device and a plurality of data processing ports connected to the internal crosspoint ports. The NSS includes a plurality of network interfaces connected to the external crosspoint ports. The data processing card processes the input data and generates processed data on the second data processing port at least in part by only including market-data packets that meet a first predetermined filtering criterion in the processed data. The crosspoint switch replicates the processed data from the second data processing port to the second network interface.

System and method for low-latency network data switching

Systems and methods are provided for measuring latency in a network device, which can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

Systems and methods for measuring latency in a network device

Method and systems for data switching, including receiving first input data at a network switching system comprising a crosspoint switch and a data processing card; transmitting the first input data from the crosspoint switch to the data processing card; making a first determination, by the data processing card, that the first input data meets a first pre-determined filtering criterion; and transmitting, based on the first determination, the first input data from a first crosspoint switch port of the crosspoint switch towards a first client.

A data processing system, method and device. A device can include a plurality of data cards having host interface connectors initially configured to transmit signals according to a first communication protocol and data card connectors that communicate with external devices using a different communication protocol. The data cards are converted so that the host interface connectors also transmit signals using the second communication protocol. The plurality of data cards are interconnected so that signals can be routed through the data cards to provide desired data processing functions. A cross-point switch fabric allows the signals to be routed to the appropriate data card or cards. Multiple devices can be interconnected to provide a distributed data processing grid providing access to the data processing functions for external devices that do not communicate using the first communication protocol.

Distributed FPGA solution for high-performance computing in the cloud

Systems and methods are provided for timestamping, which can include a signal generator, a detector, a sampler, a pulse detector, a timer, and a time-stamper. The signal generator can define a signal profile. The detector can i) detect a data event, and, upon detecting the data event, ii) instruct the signal generator to change from operating in a first mode of operation to operating in a second mode of operation. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits. The pulse detector can detect a change in the signal profile by detecting a change in value in the plurality of bits. The timer can time the change in the signal profile to provide at least one detection time measurement. The time-stamper can record in association with the data event a timestamp based on the at least one detection time measurement.

Systems and methods for timestamping a data event

Systems and methods are provided for timing signals. The systems and methods can include a signal-timing FPGA circuit. The signal-timing FPGA circuit includes a serializer, a pulse detector, at least one slower portion, a timer, and a signal generator. The serializer can convert data streams between serial transmission and parallel transmission. The serializer includes a serial input sampler for sampling signals received at the serializer, and a clock multiplier for changing signal frequencies. The at least one slower portion has a slower clock speed. The slower clock speed is slower than a clock speed of the clock multiplier. The timer is in communication with the serializer. The signal generator can generate and transmit a signal including a pulse portion and a non-pulse portion to the serializer via the at least one slower portion. The pulse portion differs in value from the non-pulse portion of the signal.

A data card enclosure method and system comprising data card connectors and host interface connectors on a data card housed in the data card enclosure. The data card enclosure method and system provided for connecting the data card connectors and host interface connectors to external communications ports.

Circuit board enclosure and method for communications applications

A physical-layer cross connect (PLCC) includes a system-bus interface; a switching circuit having multiple externally accessible data ports, an internal-only PLCC-controller port, and a data bus that is dynamically configurable among the externally accessible data ports and the internal-only PLCC-controller port; transceivers connected to the externally accessible data ports and to a signal bus; data jacks connected to the transceivers; and a PLCC controller interfaced with the system-bus interface, the data bus, the signal bus, and the internal-only PLCC-controller port and configured to: receive path-configuration commands from a communication-path-management controller and responsively configure connections on the data bus; receive mirrored copies of inbound data by selectively configuring connections on the data bus between the internal-only PLCC-controller port and the various externally accessible data ports; analyze the mirrored copies of inbound data to determine at least one informational characteristic; and report the determined informational characteristic(s) to the communication-path-management controller.

Systems and methods for implementing a physical-layer cross connect

A data card enclosure method and system comprising data card connectors and host interface connectors on a data card housed in the data card enclosure. The data card enclosure method and system provided for connecting the data card connectors and host interface connectors to external communications ports. One or more of the data card connectors may be repurposed as one or more host interface connections or one or more of the host interface connectors may be repurposed as one or more data card connectors.

System and method for repurposing communication ports as host interface or data card connections

Presently disclosed are systems and methods for identifying interconnections among physical-layer cross-connect switches. One embodiment takes the form of a method of discovering external connections among a plurality of interconnected physical-layer cross connects (PLCCs). The method includes maintaining external-link mapping data for the plurality of PLCCs, which each include a plurality of ports. The method further includes determining that a first data sequence that was transmitted outbound via a first port of a first PLCC matches a second data sequence that was received inbound via a second port of the second PLCC, and responsively updating the external-link mapping data to indicate an external connection between the first port of the first PLCC and the second port of the second PLCC.

Systems and methods for identifying interconnections among physical-layer cross-connect switches

A digital networking system includes a digital crosspoint switch, a host controller, and a data processing card that includes a programmable logic device such as a field-programmable gate array (FPGA). The host controller is operative to configure both the data processing card and the digital crosspoint switch in accordance with commands received over a user interface. The system is configurable to direct incoming data through the crosspoint switch to the data processing card for processing, and then back through the crosspoint switch for distribution to one or more network ports. The processing performed by the data processing card may include, among other options, feed filtering of a digital market data feed for use in high-frequency trading applications.

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Mississauga, Canada

Sergey Sardaryan