Amazon Technologies, Inc.

Sergey Kleyman

Adi Habusha

Guy Nakibly

Ofer Naaman

Itai Avron

Uri Leder

Dan Trock

Benny Pollak

Roi Ben Haim

Gal Kochavi

Muhamad Grefat

Ariel Pescovsky

Danny Sapoznikov

Lior Podorowski

A link layer reliability (LLR) circuit of a communication device can receive an indication that a link down event has occurred on a bus link with a peer device. The LLR circuit can prevent the link down event from triggering a reset of configuration registers containing bus settings for the bus link. Once the bus link has been restored, the LLR circuit can send a retry request to the peer device indicating an expected sequence number associated with a transaction that the LLR circuit is expecting from the peer device. The LLR circuit may receive a retry acknowledgment from the peer device indicating receipt of the retry request for the transaction corresponding to the expected sequence number, and payload data for the transaction corresponding to the expected sequence number.

Link down resilience

Systems and methods are disclosed to provide an autonomous management of communication links between dice on a multi-die assembly. Each die can include a detection unit and a controller to detect a failing communication link and perform link maintenance by directing the communication traffic on the failing link to an operational link before the link fails. Once the failing link has been repaired, the controller can re-direct the traffic back to the repaired link. The controllers on each die can negotiate through a handshake process to provide the continuous operation by switching the communication traffic from the failing link to the operational link, and then from the operational link to the repaired link.

Autonomous management of communication links

In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

Interconnect address based QoS regulation

An integrated circuit device includes multiple circuit tiles disposed in a tiled arrangement in a circuit block between a first boundary and a second boundary. Each circuit tile is an instance of a circuit cell having a first edge and a second edge. The circuit cell has a scan channel circuit that includes a configurable scan channel switch and scan channels extending between the first edge and the second edge of the circuit cell through the configurable scan channel switch. Respective scan channels in the multiple circuit tiles are joined together and extend between the first boundary and the second boundary of the block of tiled arrangement. Each circuit tile can be configured to receive scan-in test data through a scan channel from either the first boundary or the second boundary, and to output scan-out result data of the circuit tile through a scan channel to either the first boundary or the second boundary.

Scan channel fabric for tiled circuit designs

Growing community of inventors

Tel Aviv, Israel

Sergey Kleyman