Intel Corporation

Lsi Corporation

Sergey B Gashkov

Alexander Andreev

Anatoli Aleksandrovich Bolotov

Mikhail I Grinchuk

Sergey Vladimirovich Gribok

Lav D Ivanovic

Alexei Vladimirovich Galatenko

Igor V Kucherenko

Anatoly A Chasovshikh

A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.

Low depth combinational finite field multiplier

An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.

Cryptographic random number generator using finite field operations

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Moscow, Russia

Sergey B Gashkov