Sandisk Technologies Inc.

Sandisk Corporation

Western Digital Technologies, Inc.

Micron Technology Incorporated

Lexar Media, Inc.

Sergey Anatolievich Gorobets

Alan David Bennett

Liam Michael Parker

Daniel Lee Helmick

Alan Welsh Sinclair

Steven Theodore Sprouse

Peter Grayson

Shai Traister

Neil Richard Darragh

Andrew John Tomlin

Peter John Smith

William S Wu

Kevin M Conley

Chris Avila

Alan Douglas Bryce

Eugene Zilberman

Jack Frayer

Tien-Chien Kuo

Alexander Paley

Charles Michael Schroter

Yan Li

Jian Feng Chen

Carlos J Gonzalez

Daniel Edward Tuers

Jason T Lin

Ryan R Jones

Bum Suck So

Yuval Shohet

Michelle Martin

Robert George Young

Neil D Hutchison

Thomas Hugh Shippey

Eran Sharon

Idan Alrod

Alexander Bazarsky

Jianmin Huang

James Fitzpatrick

Manuel Antonio d'Abreu

Xinde Hu

Aaron Keith Olbrich

Eran Erez

Reuven Elhamias

J James Tringali

Lee M Gavens

Xinmiao Zhang

Neil David Hutchison

Yosief Ataklti

Nagi Reddy Chodem

Leena Patel

Marielle Bundukin

Neil David Hutchinson

Masaaki Higashitani

Deepanshu Dutta

Jun Wan

Seungpil Lee

Abhijeet Manohar

Kroum Stanimirov Stoev

Gautam Ashok Dusija

Seungjune Jeon

Karin Inbar

Grishma Shah

Haining Liu

Chris Nga Yee Avila

Alexander Kwok-Tung Mak

Damian Pablo Yurzola

Gary Lin

Jonathan Hsu

Gulzar Ahmed Kathawala

Alex Mak

Matthew Davidson

Uri Peltz

Yee Lih Koh

Einat Lev

Kevin Patrick Kealy

Ameen Aslam

Richard Michael Taylor

Niv Cohen

Roi Kirshenbaum

Neil A Dunlop

Robert Jackson

Alan David Bennet

Russell R Reynolds

Marc Acosta

Philip D Royall

Ofer Sharon

Natalia Victorovna Ouspenskaia

Evangelos Vazaios

Jerry Lo

Tom Hugh Shippey

Yauheni Yaromenka

The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.

TLC data programming with hybrid parity

Rather than having unused die blocks, partial die blocks can contribute to a super block. In so doing, as much of the available physical capacity of the data storage device may be achieved. The result could be an increase in over provisioning (OP) and good capacity for the data storage device or an increase in die yield. An increase in good capacity through the use of previously unused physical blocks would lead to an increase in performance and endurance. A yield increase would result in a reduction in cost per die and per data storage device. A partial die block is the solution.

Partial die blocks

A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or more failed hold-up capacitors, the controller is configured to reallocate the write buffers of the write cache for use in one or more subsequent write operations.

Hold-up capacitor failure handling in data storage devices

A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.

Read collision avoidance in sequential mixed workloads

A storage system receives a request to read data that is located in a wordline undergoing a program operation. Instead of waiting for the program operation to complete, which would increase read latency, the storage system aborts the program operation and reconstructs the data from successfully-programmed memory cells in the wordline and from data latches associated with unsuccessfully-programmed memory cells in the wordline. The reconstructed data is then sent to the host. The program abort command can be similar to one used to provide a graceful shutdown in a power-loss situation.

Storage system and method for improving read latency during mixed read/write operations

Disclosed are systems and methods detecting and isolating faulty hold-up capacitors and performing corrective actions for a data storage device. A hardware circuit is coupled to a micro-controller and non-volatile memory dies. The method includes, at the hardware circuit: providing a back-up power for the non-volatile memory dies and the micro-controller; and detecting whether a hold-up capacitor of the hardware circuit is faulty and isolating the hold-up capacitor in accordance with a detection that the hold-up capacitor is faulty. The method also includes, at the micro-controller: obtaining a status of an interface coupled to the hardware circuit; determining a status of the hardware circuit based on the status of the interface; and performing a corrective action for the data storage device in accordance with a determination that the status of hardware circuit corresponds to one or more faulty hold-up capacitors.

Detection and isolation of faulty holdup capacitors using hardware circuit in data storage devices

A non-volatile storage apparatus includes a plurality of non-volatile memory cells formed on a memory die, each non-volatile memory cell configured to hold a plurality of bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data.

Nonvolatile memory with on-chip encoding for foggy-fine programming

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM), second random access memory (RAM), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM, RAM, and the storage unit can be optimized. A temporary buffer is utilized within the RAMto update parity data for the corresponding commands. The parity data is updated in the RAMand written to the RAMin the corresponding stream. The parity data may be copied from the RAMto the RAMto update the parity data in the temporary buffer when commands are received to write data to corresponding streams. As the parity data is updated, the corresponding command is simultaneously written to the corresponding stream.

Storage devices hiding parity swapping behavior

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first parity data for the first command is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first parity data is copied from the RAM1 to a parking section in the storage unit, and second parity data associated with the second zone is copied from the parking section to the RAM1. The second parity data is then updated in the RAM1 with the data of the second command and copied to the parking section.

Data parking for ZNS devices

Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.

Multi-phased programming with balanced gray coding

Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.

Storage system and method for data protection during power loss

A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read the memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. In some cases, the recovered data may have a high bit error rate. To handle higher bit error rates, the use of soft bit data is incorporated into an encoded foggy-fine scheme.

Nonvolatile memory with encoding for foggy-fine programming with soft bits

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. The controller restricts the host to a maximum number of zones that can be in the open and active state at a time. Open zones can be switched to the closed state, and vice versa, upon a predetermined amount of time expiring. The maximum number of open zones is based on one or more amounts of time to: generate parity data, copy the parity data from the RAM2 to the RAM1, update the parity data, switch a zone from the open and active state to the closed state, and the amount of space in a temporary RAM1 buffer.

Rate limit on the transitions of zones to open

A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.

System and method of direct write and mapping of data in a non-volatile memory having multiple sub-drives

Growing community of inventors

Edinburgh, United Kingdom

Sergey Anatolievich Gorobets