Seh America, Inc.

Micron Technology Incorporated

Intel Corporation

Sergei V Koveshnikov

Oleg V Kononchuk

Zbigniew J Radzimski

Neil A Weaver

Chandra V Mouli

Haitao Liu

Guangyu Huang

Dimitrios Pavlopoulos

Douglas G Anderson

Juan E Dominguez

Ernisse S Putna

Kyle Y Flanigan

Fernando N Gonzalez

Zhenyu Lu

Timothy L Brown

Romony K San

David A Beauchaine

Howard Mollenkopf

Roger Linsday

Craig Rein

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Integrated structures containing vertically-stacked memory cells

A three dimensional stacked circuit device includes multiple decks of circuit elements, each deck including multiple tiers of circuit elements. Each deck includes a highly doped hollow channel extending through the deck. Below the first deck is a source conductor to drive activity of the circuit elements. Between each deck is a conductive stop layer that interconnects the hollow channel from one deck to the hollow channel of the deck adjacent to it. Thus, all hollow channels of all decks are electrically coupled to the source conductor.

Building stacked hollow channels for a three dimensional circuit device

Systems and techniques involving optical coatings for semiconductor devices. An implementation includes a substantially isotropic, heterogeneous anti-reflective coating having a substantially equal thickness normal to any portion of a substrate independent of the orientation of the portion.

Optical coatings

An optically tuned SLAM (Sacrificial Light-Absorbing Material) may be used in a via-first dual damascene patterning process to facilitate removal of the SLAM. The monomers used to produce the optically tuned SLAM may be modified to place an optically sensitive structure in the backbone of the SLAM polymer. The wafer may be exposed to a wavelength to which the SLAM is tuned prior to etching and/or ashing steps to degrade the optically tuned SLAM and facilitate removal.

Silicon based optically degraded arc for lithographic patterning

An improved method of determining the concentration of nitrogen within a wafer is provided. At least a portion of the nitrogen within the wafer is initially gettered to a gettering site. In order prevent the in-diffusion of nitrogen, a barrier layer is generally deposited upon the wafer prior to gettering the nitrogen within the wafer. The nitrogen is then measured at the gettering site. The concentration of nitrogen within the wafer is then determined based upon the measurement of nitrogen at the gettering site and the diffusion coefficient for nitrogen. In this regard, the diffusion coefficient of nitrogen permits the measurement of nitrogen at the gettering site to be translated into a measurement of the concentration of nitrogen throughout the entire wafer.

Method of determining nitrogen concentration within a wafer

A semiconductor wafer manufacturing is disclosed wherein an SOI wafer is produced by annealing a polysilicon layer deposited on a substrate wafer in an oxygen-containing ambient, and annealing the wafer at high temperatures to form an oxide layer at the interface of the substrate wafer and polysilicon layer. During the high temperature anneal, the polycrystalline silicon layer also recrystallizes to a monocrystalline state, and replicates the lattice structure of the substrate wafer.

Method of producing an SOI wafer

An improved method of obtaining a wafer exhibiting high resistivity and high gettering effect while preventing the reduction of resistivity due to the generation of oxygen donors provided by: a) using the CZ method to grow a silicon single crystal ingot having a resistivity of 100 &OHgr;&middot;cm or more, preferably 1000 &OHgr;&middot;cm, and an initial interstitial oxygen concentration of 10 to 40 ppma while doping the crystal with an electrically inactive material such as nitrogen, carbon, or tin, b) processing the ingot into a wafer, and c) subjecting the wafer to an oxygen precipitation heat treatment whereby the residual interstitial oxygen content in the wafer is reduced to about 8 ppma or less.

High resistivity silicon wafer having electrically inactive dopant and method of producing same

A method of obtaining a wafer exhibiting high resistivity and high gettering effect while preventing the reduction of resistivity due to the generation of oxygen donors, and while further minimizing in-grown defects is provided by: a) using the CZ method to grow a silicon single crystal ingot having a resistivity of 100 &OHgr;&middot;cm or more, preferably 1000 &OHgr;&middot;cm, and an initial interstitial oxygen concentration of 10 to 40 ppma with a v/G ratio of from about 1&times;10 cm /s&middot;K to about 5&times;10 cm /s&middot;K, b) processing the ingot into a wafer, and c) subjecting the wafer to an oxygen precipitation heat treatment whereby the residual interstitial oxygen content in the wafer is reduced to about 8 ppma or less.

High resistivity silicon wafer produced by a controlled pull rate czochralski method

A high resistivity wafer which does not exhibit diminishing resistivity after device installation and method of making the high resistivity wafer comprising a) using the CZ method to grow a silicon single crystal ingot with a resistivity of 100 &OHgr;&middot;cm or more, preferably 1000 &OHgr;&middot;cm or more, and an initial interstitial oxygen concentration of 10 to 40 ppma, b) processing the ingot into a wafer, c) determining the total amount of heat treatment required to reduce the interstitial oxygen content of the wafer to about 8 ppma or less, d) determining the amount of heat treatment which will take place during the device fabrication process after wafer fabrication, e) subjecting the wafer to a partial oxygen precipitation heat treatment equivalent to the total amount of heat treatment, less the amount of heat treatment that will occur during device fabrication.

Method of producing a high resistivity silicon wafer utilizing heat treatment that occurs during device fabrication

A method for non-destructively evaluating the concentration of impurities in an epitaxial susceptor used in the processing of a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels on the epitaxial susceptor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Method for evaluating impurity concentrations in epitaxial susceptors

A method for evaluating the concentration of impurities in gases used in depositing an epitaxial layer on a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels in an epitaxial reactor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Method for evaluating impurity concentrations in epitaxial reagent gases

A method for evaluating the concentration of impurities in as-grown monocrystalline semiconductor ingots is provided. The method includes growing a monocrystalline semiconductor ingot, and measuring the bulk impurity levels of the ingot by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of a sample of the monocrystalline semiconductor ingot to getter impurities from the sample into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were grown into the monocrystalline semiconductor ingot.

Growing community of inventors

Vancouver, WA, United States of America

Sergei V Koveshnikov