Lsi Corporation

Lsi Logic Corporation

Sergei B Gashkov

Alexander Andreev

Anatoli Aleksandrovich Bolotov

Mikhail I Grinchuk

Lav D Ivanovic

Elyar Eldarovich Gasanov

Andrey Nikitin

Pavel Anatolyevich Panteleev

Ilya Vladimirovich Neznanov

Alexandre Andreev

Oleg B Sedelev

An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.

Universal Galois field multiplier

An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.

Low depth programmable priority encoders

An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t&#x2212;1)/(codeword_len&#x2212;3)&#x2266;X&#x3c;(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Low area architecture in BCH decoder

An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvement comprising only one write address decoder, and replacing the read address decoder and the set of AND gates and the set of OR gates with no more than one multiplexor, thereby providing a reduction in a path length from an rcell memory input to an rcell memory output and thereby improving timing of the rcell memory, while reducing fanout size of the rcell. In a preferred embodiment, the multiplexor includes fewer than w OR gates, and fewer than n AND gates, and two decoders, which are commonly connected to outputs of the n flip flops.

RRAM flipflop rcell memory generator

A method for constructing a logic circuit for inversion in finite field GF(2) is described, where m=nk, and k, n are coprime numbers, using bases in subfields GF(2) and GF(2). The method may be applied to error correction codes, including BCH codes, Reed-Solomon codes (which are a subset of BCH codes), turbo codes, and the like.

Growing community of inventors

Moscow, Russia

Sergei B Gashkov