Intel Corporation

Serge Kornfeld

Donald F Hooper

James D Guilford

Debra Bernstein

William Ralph Wheeler

Robert P Ottavi

Richard D Muratori

Desmond R Johnson

Lai-Wah Hui

John C Cole

A method and apparatus for transmitting network traffic includes selecting a major node in a major ring, where the major node corresponds to a first transmission opportunity encoded in the major ring. The major node specifies a minor node in a minor ring representing a virtual port. The method and apparatus also includes transmitting network traffic to a virtual connection that uses the virtual port. Alternatively, transmitting network traffic involves processing a schedule that includes a sequence of transmission opportunities encoded in a schedule ring and satisfying a minimum data rate for a scheduled virtual connection by processing a corresponding first minimum number of transmission opportunities from the schedule, each such transmission opportunity allocated by a schedule node to the scheduled virtual connection, where the schedule node is included in the schedule ring.

DSL transmit traffic shaper structure and procedure

A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.

Breakpoint method for parallel hardware threads in multithreaded processor

Applications software can be rapidly tested and developed for a multi-processor chip even though the hardware of new processors of the multi-processor chip is not yet available. This can be accomplished by executing software simulations of the new processor designs and corresponding applications software either on a previously designed processor that is hardware on the multi-processor chip or on a workstation development platform. The execution of the previously designed processor is typically much faster than the execution on a simulator running on a personal workstation development platform, and therefore the execution time is quicker. Furthermore, the processor simulation and application software can be configured to take advantage of the platform most appropriate for execution and avoid simulation of portions of the new processors that are not necessary for testing the applications software.

Apparatus and method of developing software for a multi-processor chip

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Westborough, MA, United States of America

Serge Kornfeld