Nxp B.v.

Philips Electronics North America Corporation

Philips Electronics North America Corporaiton

Serge Bardy

Gilles Marcel Ferru

Chun-Yu Chen

Gian Hoogzaad

Gilles Ferru

Olivier Crand

Robert Victor Buytenhuijs

Lucie A Rousseville

Philippe Le Duc

Luuk F Tiemeijer

David Desmortreux

Yann Bouttement

An attenuator arrangement comprising at least a first attenuation path configured to couple between a signal processing chain, SPC, and a measurement apparatus; said SPC comprising a first and second SPC terminal, said SPC configured to apply one or both of a gain and phase change on a signal passed between the SPC terminals; said measurement apparatus configured to measure one or both of the gain and the phase change applied by SPC by coupling to and receiving signals from said SPC terminals; wherein one of said first SPC terminal and said second SPC terminal is coupled to the measurement apparatus through said first attenuation path; and wherein the at least first attenuation path of the attenuator arrangement is configured to provide, selectively, for attenuation of the signal to the measurement apparatus to make the signal power of the signals from said SPC terminals more equal.

Attenuator arrangement

A device for switchably routing down-converted radio frequency (RF) signals from a plurality of inputs to a plurality of outputs, and a method of operating the same. The device includes a respective switch for each output. The device also includes an interconnect arrangement. The interconnect arrangement includes a respective transmission line for each input. Each transmission line includes a plurality of branches for routing a down-converted RF signal received at the input of that transmission line to the switch of each output. The switch of each output is operable selectively to connect one of the transmission lines to its output. The interconnect arrangement also includes a plurality of cross-over points at which two of the branches cross over each other.

Device and method for switchably routing down-converted RF signals

Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area. The semiconductor device includes a first test structurefor determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the common contact areas. The first test structure includes a pad metal layer portionand a metallization layer portionbeing in electrical communication with the pad metal layer portionthrough the common contact area. The first test structurefurther includes connection areasthat are electrically connected with each other substantially via the common contact area. Upon application of a current between the connection areasa voltage drop occurs that is representative for a voltage drop over the common contact area

Semiconductor device and wafer with a test structure and method for assessing adhesion of under-bump metallization

An electronic device is made from a first substrate with device circuitry including an inductor and a second substrate with inductance adjustment circuitry including a number of other inductors. The substrates are assembled together to be opposite one another. The other inductors are arranged to provide a selection of different mutual inductance relationships relative to the inductor. These relationships are selectable during operation of the device to provide a variable inductance in the device circuitry.

Variable inductance circuitry for frequency control of a voltage countrolled oscillator

A method of providing a region of doped semiconductor () which is buried below the surface of a semiconductor substrate () without the requirement of epitaxially deposited layers is provided. The method includes the steps of forming first and second trench portions () in a semiconductor substrate and then introducing dopant () into the trench portions and diffusing the dopant into the semiconductor substrate such that a region of doped semiconductor () is formed extending from the first trench portion to the second trench portion. A diffusion barrier, for example formed of two barrier trenches (), is provided in the substrate adjacent the doping trenches to inhibit lateral diffusion of dopant from the doping trenches so as to maintain an undoped region () above the region of doped semiconductor. Advantageously, the electrical properties of the buried layer can be adjusted by varying the depths and size/spacing of the doping trenches and diffusion barrier(s), and the doping and diffusion parameters. The doping trenches can later be filled with polysilicon to provide electrical contact to the buried doped region.

Method of manufacturing a semiconductor device having a buried doped region

An integrated injection logic device is provided in which each collector of an I,L gate is isolated by a field oxide (&ldquo;FOX&rdquo;), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN,in the Figures illustrating the invention). Because both silicide and heavy implant p&plus; implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside own NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e. one can adjust the base to collector areas and the base contact area, independently to control the total base current, thus allowing more freedom in layout optimization of the I,L gate and allowing more freedom in optimizing the gain of the I,L gate.

Method of forming isolated integrated injection logic gate

An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ('FOX'), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside down NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e. one can adjust the base to collector areas and the base contact area, independently to control the total base current, thus allowing more freedom in layout optimization of the I2L gate and allowing more freedom in optimizing the gain of the I2L gate.

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Caen, France

Serge Bardy