International Business Machines Corporation

Serafin J Garcia, Jr

Gary B Hoch

Eric H Stelzer

Donald G Williams

Dean Alan Kalman

Don S Keener

Douglas R Chisholm

Arthur L Chin

Robert Dean Yoder

Gregory J Moore

Russell S Padgett

Stephanie P Payne

Eric S Stine

Michael S Gatson

A digital bus circuit having an Address/Data port select decoder 170 in circuit communication with a Selector 194, a Data Port Buffer/Register 181, and an Address Port register 208. The Selector 194 is in circuit communication with an auto incrementor 216, an auto decrementor 218, and a polling function. The incrementor 216 serves to automatically increment an address present in the Address port register 208. The decrementor 218 serves to automatically decrement an address present in the Address port register 208. The polling function serves to reload the Address port register 208 with the same address. The present invention allows a number of enhanced programming methods which permit input and output operations to be implemented with fewer program code instructions. One of the programming methods disclosed by the present invention is an enhanced method of 'polling' a device's internal register by accessing the polling function.

Digital I/O bus controller circuit with auto-incrementing,

DMA adapters which perform programmed data transfer operations in response to descriptors are programmed by information in the same descriptors (and adapter logic responsive to that information) to perform various ancillary control functions relative to addressable I/O devices that conventionally would be addressed and controlled directly by a host (higher level) system processor (e.g., the processor that prepares the descriptors). The ancillary control functions are variable programmably in number (e.g., in the disclosed embodiment, one descriptor can define 0, 1 or 2 discrete ancillary control operations) and effects produced by each operation are programmably variable (e.g., ancillary operation can be used by the adapter to alter states of addressed devices; for example, to prepare a device that has been transferring data in one direction, in a half-duplex mode, for transferring data in the opposite direction, or to switch to a full duplex mode, etc.). These functions hitherto have imposed significant processing burdens on the host processor and functional constraints on the adapters and devices; typically, constraints requiring the adapter and one or more devices to be idled for the time required by the host to condition the device(s). Accordingly, delegation of these functions to the adapter, allows them to be carried out without idling of any system elements and while the host is otherwise productively occupied. Also, such delegation creates new applicational possibilities; e.g., having an adapter linked to a communication channel react to remotely originated signals and set up operations tightly coordinated in real time to previously executed operations (for example, retransmission of data previously received with detected error).

Computer I/O adapters for programmably varying states of peripheral

A processor stores descriptors without explicit linkages, in non-contiguous memory locations, and sequentially hands them off to an adaptor which manages scheduling and processing of data transfers defined by the descriptors. Each descriptor is handed off in a request signalling process in which the processor polls the availability of a request register in the adaptor, and writes the address of a respective descriptor to that register when it is available. The adapter then schedules processing of the descriptor whose address is in the request register. The adapter manages a 'Channel Descriptor Table' (CDT), which defines the order of processing of descriptors designated by the requests. In effect, the CDT defines a linked list queue into which the adapter installs descriptors, in the sequence of receipt of respective requests. Using the CDT information, the adapter retrieves successively queued descriptors and controls performance of operations (data transfer or other) defined by them. Accordingly, descriptors in the queue are retrieved and respectively defined operations are performed, in the order of receipt of respective requests; as if the descriptors had been stored by the processor with explicit linking and chaining associations and handed off to the adapter as an explicitly chained set of descriptors. In a preferred embodiment, a 'multichannel adapter unit' (MAU), directing data transfers relative to multiple channels, contains one request register for all channels and a separate CDT and 'request address port' dedicated to each channel. Requests accompanied by addresses designating these ports are 'funneled' through the request register to CDT queues of respective channels. The processor can effectively remove a descriptor from any CDT queue, without potentially compromising handling of data transfers defined by other descriptors in the queue, by writing a 'skip code' to the descriptor. Upon retrieving a descriptor with a skip code, the adapter automatically skips the operation defined by that descriptor and chains to a next descriptor (if the queue defined by the CDT is not empty).

Adapters with descriptor queue management capability

A plurality of specialized controllers (e.g., 202, 204 & 206), each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus (104) and a local bus (106) on a computer adapter card (102). When the Direct Memory Access (DMA) controller (202) is controlling a DMA operation on the local bus, certain other controllers (204 & 206) can break-in to the current DMA operation, temporarily halting the DMA opertion until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit (212) are temporarily blocked by blocking signals from a break-in logic circuit (210). The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

Bus master interface circuit with transparent preemption of a data

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Boynton Beach, FL, United States of America

Serafin J Garcia, Jr