Sun Microsystems, Inc.

Picocraft Design Systems, Inc.

Ser-Hou Kuang

Samir S Palnitkar

Guillermo Maturana

Chee-Keng Chang

Tim Bucher

Prasad V Saggurti

Sean Kevin Murphy

Howard Landman

A method for analyzing and validating clock integration properties in a circuit design is disclosed. A database of timing points that are clocked cell elements of the circuit design is generated. Next, a timing point frame showing the interaction of the clocked cell elements and the non-clocked cell elements is generated. The timing point frame graphically shows the timing network properties for the cell elements of the circuit design. A clock analysis view can be generated from the timing point frame for selected timing points. In this respect, the timing point frame shows timing points that meet a prescribed criteria (e.g., same clock domain). Therefore, the clock analysis view provides a graphical representation of timing and clock interactions for the circuit design.

Method for analyzing and validating clock integration properties in circuit systems

A computer system for generating a summary of test coverage for a hardware description. The hardware description corresponds to a finite state machine (FSM). This embodiment requires at least one test vector. The computer system comprises a memory and a processor. The memory is for storing the hardware description and the test vector. The processor, coupled to the memory, uses the hardware description and generates state information corresponding to the FSM. The processor, using the state information, further generates a first description. The first description includes a description for monitoring states and signals in the hardware description. The processor, using the test vector, the hardware description and the first description, further generates the test coverage summary.

Method and apparatus for analyzing finite state machines

The method of the present invention includes steps wherein a circuit designer, using standard computer assisted design (CAD) tools, designs a circuit which may include multi-cycle paths (MCPs). The designer inserts a conceptual circuit element, referred to as a 'path breaker' into multi-cycle paths, such that the result is to convert all multi-cycle paths into single cycle paths. The designer then utilizes functional simulation software to edit the circuit design. To the simulator, a path breaker appears to be a latch in which the latch output goes to an unknown state when the input changes, and remains so until the output has been clocked and is equal to the input. Traditional logic synthesis is then performed on the circuit such that a net list is generated which includes the path breakers. Based on the net list, a post processor determines where in the circuit multi-cycle paths exist and generates a net list without path breakers, as well as a list of the multi-cycle paths. The list of multi-cycle paths is provided to a static path analysis program where the locations of the multi-cycle paths denote exceptions. Timing analysis is then performed, and if the circuit is satisfactory, fabrication may be completed using the net list without the conceptual path breakers.

Method and apparatus to improve static path analysis of digital circuits

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San Jose, CA, United States of America

Ser-Hou Kuang