Tritech Microelectronics, Ltd

Other

Seppo Ingalsuo

Tapani Ritoniemi

Eero Pajarre

Ville Eerola

Timo Husu

Tapio Saramaki

Tapio Saram&auml;ki

The invention relates to a method and an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients, and to a method for designing such a filter. The invention comprises a shift register ( ) shifting in the direction of the least significant bit and copying the most significant bit or filling in zero values. The register receives the binary input signal of the filter and has outputs for outputting the content of the desired bit positions. A plurality of bit-serial subtractor and adder elements ( ) multiply the binary input signal by N&plus;1 different tap coefficients by combining output bits of the shift register ( ). The subtractor and/or adder elements form a network wherein at least one element participates in the multiplying operation of at least two different tap coefficients.

Method and arrangement in a transposed digital FIR filter for multiplying a binary input signal with tap coefficients and a method for designing a transposed digital filter

Calculation of a scalar product in a direct-type FIR filter

Decimation filter

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Tampere, Finland

Seppo Ingalsuo