Samsung Electronics Co., Ltd.

Seouk-Kyu Choi

Jong-Hyun Choi

Nam-Jong Kim

Il-Man Bae

Woo-Pyo Jeong

In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Method of operating a semiconductor device and the semiconductor device

A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

Tri-state output driver arranging method and memory device using the same

A level shifter for level shifting an input signal from a first level to an output signal having a second level includes an operation range extension portion configured to extend an input range of the level shifter and to generate a first extension control signal in response to the input signal and a second extension control signal in response to an inverted version of the input signal, an output control portion configured to generate an output control signal in response to the input signal, the first extension control signal, and the output signal, and an output portion configured to generate the output signal in response to the inverted version of the input signal, the second extension control signal, and an output control signal.

Level shifter having extended input level

A speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Growing community of inventors

Hwasung-si, South Korea

Seouk-Kyu Choi