Intel Corporation

Seongtae Jeong

Shem Ogadhoh

Vivek K Singh

Bikram Baidya

Bin Hu

Sungwon Kim

Raguraman Venkatesan

Kevin J Hooker

Prasad Narendra Atkar

Charles Henry Wallace

Manish Chandhok

Swaminathan Sivakumar

Paul Anton Nyhus

Yan A Borodovsky

Andrew W Yeoh

Zhanping Chen

Allen B Gardiner

Uddalak Bhattacharya

Chris Kenyon

Marie T Conte

Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.

Necked interconnect fuse structure for integrated circuits

Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

Techniques for phase tuning for process optimization

Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

Mask design and OPC for device manufacture

A scattered light point spread function is measured for use in fabricating microelectronic and micromechanical devices using photolithography. In one example, a photosensitive layer of a microelectronic substrate is exposed through a test mask, the test mask having a series of differently sized patterns, each pattern surrounding a central monitor feature, the differently sized patterns each being evenly distributed about its respective central monitor feature. An indication of the exposure of the photosensitive layer is measured for a plurality of the series of differently sized patterns. The exposure indication is compared to the pattern size. The comparison is fitted to a function and the function is applied in correcting photolithography mask layouts.

Measurement of a scattered light point spread function (PSF) for microelectronic photolithography

Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.

Test structures for feature fidelity improvement

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Portland, OR, United States of America

Seongtae Jeong